Isamu Kajitani

Real-world applications of analog and digital evolvable hardware

In contrast to conventional hardware where the structure is irreversibly fixed in the design process, evolvable hardware (EHW) is designed to adapt to changes in task requirements or changes in the environment, through its ability to reconfigure its own hardware structure dynamically and autonomously. This capacity for adaptation, achieved by employing efficient search algorithms based on the metaphor of evolution, has great potential for the development of innovative industrial applications. This paper introduces EHW chips and six applications currently being developed as part of MITIs Real-World Computing Project; an analog EHW chip for cellular phones, a clock-timing architecture for Giga hertz systems, a neural network EHW chip capable of autonomous reconfiguration, a data compression EHW chip for electrophotographic printers, and a gate-level EHW chip for use in prosthetic hands and robot navigation.

Hardware Evolution at Function Level

This paper describes a function-level Evolvable Hardware (EHW). EHW is hardware which is built on programmable logic devices (e.g. PLD and FPGA) and whose architecture can be reconfigured by using a genetic learning to adapt to new unknown environments in real time. It is demonstrated that the function-level hardware evolution can attain much higher performances than the gate-level evolution, in neural network applications (e.g. two-spiral). VLSI architecture of the functionbased FPGA dedicated to function level evolution is also described.

Evolvable Hardware and Its Applications to Pattern Recognition and Fault-Tolerant Systems

This paper describes Evolvable Hardware (EHW) and its applications to pattern recognition and fault-torelant systems. EHW can change its own hardware structure to adapt to the environment whenever environmental changes (including hardware malfunction) occur. EHW is implemented on a PLD(Programmable Logic Device)-like device whose architecture can be altered by re-programming the architecture bits. Through genetic algorithms, EHW finds the architecture bits which adapt best to the environment, and changes its hardware structure accordingly.

A Gate-Level EHW Chip: Implementing GA Operations and Reconfigurable Hardware on a Single LSI

The advantage of Evolvable Hardware (EHW) over traditional hardware is its capacity for dynamic and autonomous adaptation, which is achieved through by Genetic Algorithms (GAs). In most EHW implementations, these GAs are executed by software on a personal computer (PC) or workstation (WS). However, as a wider variety of applications come to utilize EHW, this is not always practical. One solution is to have the GA operations carried out by the hardware itself, by integrating these together with reconfigurable hardware logic like PLA (Programmble Logic Array) or FPGA (Field Programmable Gate Array) on to a single LSI chip. A compact and quickly reconfigurable EHW chip like this could service as an off-the-shelf device for practical applications that require on-line hardware reconfiguration. In this paper, we describe an integrated EHW LSI chip that consists of GA hardware, reconfigurable hardware logic, a chromosome memory, a training data memory, and a 16-bit CPU core (NEC V30). An application of this chip is also described in a myoelectric artificial hand, which is operated by muscular control signals. Although, work on using neural networks for this is being carried out, this approach is not very promising due to the long learning period required for neural networks. A simulation is presented showing that not only is the EHW performance slightly better than with neural networks, but that the learning time is considerably reduced.

A Pattern Recognition System Using Evolvable Hardware

We describe a high-speed pattern recognition system using Evolvable Hardware (EHW), which can change its own hardware structure by genetic learning in order to adapt best to the environment. The purpose of the system is to show that EHW can work as a recognition device with such robustness for the noise as seen in the recognition systems based on neural networks. The advantage of EHW compared with a neural network is the high processing speed and the readability of the learned result. The readability means that the result is understandable in terms of Boolean functions. In this paper, we describe the architecture, the learning algorithm and the experiment on the pattern recognition system using EHW.

The GRD chip: genetic reconfiguration of DSPs for neural network processing

This paper describes the GRD (Genetic Reconfiguration of DSPs) chip, which is evolvable hardware designed for neural network applications. The GRD chip is a building block for the configuration of a scalable neural network hardware system. Both the topology and the hidden layer node functions of a neural network mapped on the GRD chips are dynamically reconfigured using a genetic algorithm (GA). Thus, the most desirable network topology and choice of node functions (e.g., Gaussian or sigmoid function) for a given application can be determined adaptively. This approach is particularly suited to applications requiring the ability to cope with time-varying problems and real-time constraints. The GRD chip consists of a 100 MHz 32-bit RISC processor and 15 33 MHz 16-bit DSPs connected in a binary-tree network. The RISC processor is the NEC V830 which executes mainly the GA. According to chromosomes obtained by the GA, DSP functions and the interconnection among them are dynamically reconfigured. The GRD chip does not need a host machine for this reconfiguration. This is desirable for embedded systems in practical industrial applications. Simulation results on chaotic time series prediction are two orders of magnitude faster than on a Sun Ultra 2.

Variable length chromosome GA for evolvable hardware

This paper proposes the variable-length chromosome GA (VGA) for hardware evolution. VGA is introduced for the evolvable hardware (EHW) which can change its own hardware structure by genetic learning to adapt best to the environment. VGA makes it possible to evolve larger circuits more quickly than simple GAs. The improvements by VGAs are demonstrated by two experiments; one is the evolution of combinatorial circuits, the other is the evolution of pattern classifier functions used in the pattern recognition system for hand-written inputs.

Evolvable hardware with genetic learning

This paper describes Evolvable Hardware (EHW) with genetic learning. EHW is hardware which is built on programmable logic devices (e.g. PLD and FPGA) and whose architecture can be reconfigured by using genetic learning to adapt to the new environment. There are two types of hardware evolutions; gate-level and function-level. As examples of gate-level evolution, a pattern recognition system and a welding robot controller are described. Then, function-level EHW is introduced. It is demonstrated that function-level hardware evolutions can attain high performances as in neural network applications (e.g. two spirals). New FPGA architecture for function-level evolution is also described.

Humanoid robot as an evaluator of assistive devices

This paper presents a basic study on feasibility of usage of humanoid robots as an evaluator of assistive devices, by taking advantage of its anthropomorphic shape. In this new application humanoid are expected to help evaluation through quantitative measures, which is difficult with human subjects, and also to reduce the burden coming from ethical concerns with costly tests by human subjects. Taking a passive supportive wear “Smart Suit Lite” designed to relieve the load at lower back as an example, we have conducted pilot experiments by using the humanoid robot HRP-4C. The motion to be performed by the humanoid is obtained through retargeting technique from measured human lifting motion. The supportive effect is first estimated by simulation taking into account the mechanism of the supportive device. The experimentation of humanoid hardware brought us encouraging results on the basic feasibility of this application, as we observed a clear decrease of the torque for lifting when wearing the device as expected by the simulation.

An evolvable hardware chip for prosthetic hand controller

This paper describes an Evolvable Hardware (EHW) chip, and the application of this chip as a controller for a myoelectric prosthetic hand. The chip consists of Genetic Algorithm (GA) hardware, reconfigurable hardware logic, a chromosome memory, a training data memory, and a 16-bit CPU core (NEC V30). This paper also briefly introduces other EHW chips being developed as part of the Ministry of International Trade and Industrys (MITI) Real World Computing Project (RWCP), which include an analogue EHW chip for cellular phones, a neural network EHW chip capable of autonomous reconfiguration, and a data compression EHW chip for electrophotographic printers.