Nobuki Kajihara

Real-world applications of analog and digital evolvable hardware

In contrast to conventional hardware where the structure is irreversibly fixed in the design process, evolvable hardware (EHW) is designed to adapt to changes in task requirements or changes in the environment, through its ability to reconfigure its own hardware structure dynamically and autonomously. This capacity for adaptation, achieved by employing efficient search algorithms based on the metaphor of evolution, has great potential for the development of innovative industrial applications. This paper introduces EHW chips and six applications currently being developed as part of MITIs Real-World Computing Project; an analog EHW chip for cellular phones, a clock-timing architecture for Giga hertz systems, a neural network EHW chip capable of autonomous reconfiguration, a data compression EHW chip for electrophotographic printers, and a gate-level EHW chip for use in prosthetic hands and robot navigation.

A Gate-Level EHW Chip: Implementing GA Operations and Reconfigurable Hardware on a Single LSI

The advantage of Evolvable Hardware (EHW) over traditional hardware is its capacity for dynamic and autonomous adaptation, which is achieved through by Genetic Algorithms (GAs). In most EHW implementations, these GAs are executed by software on a personal computer (PC) or workstation (WS). However, as a wider variety of applications come to utilize EHW, this is not always practical. One solution is to have the GA operations carried out by the hardware itself, by integrating these together with reconfigurable hardware logic like PLA (Programmble Logic Array) or FPGA (Field Programmable Gate Array) on to a single LSI chip. A compact and quickly reconfigurable EHW chip like this could service as an off-the-shelf device for practical applications that require on-line hardware reconfiguration. In this paper, we describe an integrated EHW LSI chip that consists of GA hardware, reconfigurable hardware logic, a chromosome memory, a training data memory, and a 16-bit CPU core (NEC V30). An application of this chip is also described in a myoelectric artificial hand, which is operated by muscular control signals. Although, work on using neural networks for this is being carried out, this approach is not very promising due to the long learning period required for neural networks. A simulation is presented showing that not only is the EHW performance slightly better than with neural networks, but that the learning time is considerably reduced.

The GRD chip: genetic reconfiguration of DSPs for neural network processing

This paper describes the GRD (Genetic Reconfiguration of DSPs) chip, which is evolvable hardware designed for neural network applications. The GRD chip is a building block for the configuration of a scalable neural network hardware system. Both the topology and the hidden layer node functions of a neural network mapped on the GRD chips are dynamically reconfigured using a genetic algorithm (GA). Thus, the most desirable network topology and choice of node functions (e.g., Gaussian or sigmoid function) for a given application can be determined adaptively. This approach is particularly suited to applications requiring the ability to cope with time-varying problems and real-time constraints. The GRD chip consists of a 100 MHz 32-bit RISC processor and 15 33 MHz 16-bit DSPs connected in a binary-tree network. The RISC processor is the NEC V830 which executes mainly the GA. According to chromosomes obtained by the GA, DSP functions and the interconnection among them are dynamically reconfigured. The GRD chip does not need a host machine for this reconfiguration. This is desirable for embedded systems in practical industrial applications. Simulation results on chaotic time series prediction are two orders of magnitude faster than on a Sun Ultra 2.

Evolvable hardware chips for industrial applications

I n contrast to conventional hardware, in which the structure is irreversibly fixed in the design process, evolvable hardware is designed to adapt, as the chameleon changes its color to blend in with the environment, to changes in task requirements or in the environment, through its ability to reconfigure its own hardware structure dynamically and autonomously. This capacity for adaptation, achieved by employing efficient search algorithms known as genetic algorithms, has great potential for the development of innovative industrial applications. Although the concept of EHW is relatively new, some EHW chips are already being evaluated for their commercial value. In this article, we introduce four

An evolvable hardware chip for prosthetic hand controller

This paper describes an Evolvable Hardware (EHW) chip, and the application of this chip as a controller for a myoelectric prosthetic hand. The chip consists of Genetic Algorithm (GA) hardware, reconfigurable hardware logic, a chromosome memory, a training data memory, and a 16-bit CPU core (NEC V30). This paper also briefly introduces other EHW chips being developed as part of the Ministry of International Trade and Industrys (MITI) Real World Computing Project (RWCP), which include an analogue EHW chip for cellular phones, a neural network EHW chip capable of autonomous reconfiguration, and a data compression EHW chip for electrophotographic printers.

Implementation of a Gate-Level Evolvable Hardware Chip

Evolvable hardware (EHW) is hardware that can change its own circuit structure by genetic learning to achieve maximum adaptation to the environment. In conventional EHW, the learning is executed by software on a computer. However, there are problems associated with this method, of slow learning speeds and large systems, which are serious obstacles to utilizing EHW in various kinds of practical applications. To overcome these problems, we have developed a gate-level evolvable hardware chip, by integrating both GA hardware and reconfigurable hardware within a single LSI chip. The chip consists of genetic algorithm (GA) hardware, reconfigurable hardware logic, and the control logic. With this chip, we have successfully executed GA learning and hardware reconfiguration. In this paper, we describe the architecture, functions, and a performance evaluation of the chip. We show that its learning speed is considerably faster than with software.

Mapping algorithms for a multi-bit data path processing reconfigurable chip RHW

While FPGAs are mainly used for implementing general purpose logic circuits, the RHW works with the CPU to accelerate the computation intensive part of the application by reconfiguring its data paths and ALUs optimized for the algorithm. Hence the RRW was designed to implement multi-bit data paths and ALUs efficiently. We developed a new architecture that consists of a two-dimensional array of multi-bit original ALU that is composed of a type of adder with multi-functional pre-logics.

Arithmetic Operation Oriented Reconfigurable Chip: RHW

We have developed an ALU based reconfigurable device called RHW (Reconfigurable HardWare) that is designed to work with the CPU to accelerate the computation-intensive part of the application by reconfiguring its data paths and ALUs optimized for the algorithm. It is also important to develop high performance operation unit library to utilize function cells of RHW efficiently. This paper describes the basic architecture of the RHW, high performance operation unit library and evaluation results.

Evolvable Hardware Chips for Neural Network Applications

This paper introduces two Evolvable Hardware LSIs for neural network applications. They are developed as part of MITI’s Real World Computing Project. One is self-reconfigurable neural network chip for ontogenic neural network processing, having the processing capability equivalent to 10 Pentium II chips. The other LSI is for the pattern recognition for myoelectric artificial hand control.

MAN-YO: Mixed level parallel logic simulation engine

MAN-YO is a special-purpose parallel computing machine being developed for logic circuit design and simulation. It uses dedicated hardware to increase the speed of gate-level simulation, and a combination of dedicated microprograms and processors for functional level simulation. Furthermore, a multiprocessor architecture, interconnected by a loop-network, is used to provide concurrent processing capability for high performance, multilevel logic simulation. Experiments were conducted to assess the performance of the functional level simulation.