Ismail Cevik

An Ultra-Low Power CMOS Image Sensor with On-Chip Energy Harvesting and Power Management Capability

An ultra-low power CMOS image sensor with on-chip energy harvesting and power management capability is introduced in this paper. The photodiode pixel array can not only capture images but also harvest solar energy. As such, the CMOS image sensor chip is able to switch between imaging and harvesting modes towards self-power operation. Moreover, an on-chip maximum power point tracking (MPPT)-based power management system (PMS) is designed for the dual-mode image sensor to further improve the energy efficiency. A new isolated P-well energy harvesting and imaging (EHI) pixel with very high fill factor is introduced. Several ultra-low power design techniques such as reset and select boosting techniques have been utilized to maintain a wide pixel dynamic range. The chip was designed and fabricated in a 1.8 V, 1P6M 0.18 µm CMOS process. Total power consumption of the imager is 6.53 µW for a 96 × 96 pixel array with 1 V supply and 5 fps frame rate. Up to 30 μW of power could be generated by the new EHI pixels. The PMS is capable of providing 3× the power required during imaging mode with 50% efficiency allowing energy autonomous operation with a 72.5% duty cycle.

An Ultra-Low Power Energy Harvesting and Imaging (EHI) Type CMOS APS Imager With Self-Power Capability

A novel ultra-low power energy harvesting and imaging (EHI) type CMOS active pixel sensor (APS) imager with self-power capability is presented. The proposed EHI type CMOS APS pixel harvests one order of magnitude higher power than that of the other pixel technologies reported in the literature. It produces 46 μW of power under 57 klux illumination. The EHI imager presented has decoupled imaging and harvesting operations such that imaging related circuits are turned off while energy is harvested, and vice versa. The imager can operate on 1 V supply voltage consuming as low as 800 nW while capturing 1 frame per second (fps). Measured minimum full-chip imager FoM is 148 pJ/frame*pixel while capturing 21.2 fps. The imager contains a 64 × 45 array of 18 μm×18 μm EHI pixels. It is manufactured in a standard 2P4M/3.3 V 0.35 μm CMOS process. Ultra-low power operation is achieved by developing new imaging electronics including current reference generator, readout circuits, and SAR type, 8-bit, analog-to digital converter (ADC). A new polarity inverting charge pump circuit was developed for managing the energy harvested by the new energy harvesting pixels on the focal plane.

A Low-Power and Low-Voltage Power Management Strategy for On-Chip Micro Solar Cells

Fundamental characteristics of on-chip micro solar cell (MSC) structures were investigated in this study. Several MSC structures using different layers in three different CMOS processes were designed and fabricated. Effects of PN junction structure and process technology on solar cell performance were measured. Parameters for low-power and low-voltage implementation of power management strategy and boost converter based circuits utilizing fractional voltage maximum power point tracking (FVMPPT) algorithm were determined. The FVMPPT algorithm works based on the fraction between the maximum power point operation voltage and the open circuit voltage of the solar cell structure. This ratio is typically between 0.72 and 0.78 for commercially available poly crystalline silicon solar cells that produce several watts of power under typical daylight illumination. Measurements showed that the fractional voltage ratio is much higher and fairly constant between 0.82 and 0.85 for on-chip mono crystalline silicon micro solar cell structures that produce micro watts of power. Mono crystalline silicon solar cell structures were observed to result in better power fill factor (PFF) that is higher than 74% indicating a higher energy harvesting efficiency.

A 0.8V 140nW low-noise energy harvesting CMOS APS imager with fully digital readout

This paper presents a novel CMOS active pixel sensor (APS) imager with fully digital global readout channel and continuous time on-chip energy harvesting. Imager captures low-noise images while consuming 140nW of power at 0.7 FPS. Imager has a 0.078% total FPN in dark. It generates 31μW power at bright daylight.

A fast two-step coarse-fine calibration (CFC) technique for precision comparator design

A two-step offset correction technique for high precision comparator design is proposed. The two step coarse-fine calibration (CFC) technique provides precise offset correction much faster than a single step calibration and the circuit implementation is less complicated. The proposed two step calibration technique was employed on a two-stage dynamic latched comparator using 0.35μm CMOS process. The post layout simulations shows that the proposed technique improves the correction precision 15 times compared to a single stage offset correction while requiring less die area, correction cycles, and calibration time.

A low power maximum power point tracker and power management system in 0.5µm CMOS

This paper presents a low-power maximum power point tracker (MPPT) and power management system (PM) for energy harvesting devices, including micro-photovoltaic (PV) cells, integrated in a 0.5 μm 2P3M CMOS process. The MPPT utilizes the fractional open circuit method which approximates the optimal operating voltage of the PV cell as a fixed fraction of the cells open circuit voltage. The proposed system uses an inductive boost converter with off-chip inductor and a novel charge skimming regulator (CSR) structure to simultaneously generate 1.8 V and 1.2V supplies which are stored in supercapacitors. The PM manages the system supply according to available resources. The total power consumption of the chip was measured to be 11.3 μW.

Power generation capability of CMOS image sensors with on-chip energy harvesting pixels

This paper presents a review of energy harvesting image sensor designs in CMOS technology. Two CMOS image sensors with on-chip energy harvesting capability are presented. Quantitative comparison of power generation capacity of these two different topologies is provided. Both structures make use of the photoelectric conversion capability of the photodiode pixel array and reconfigure the array to harvest the solar energy. The first pixel is an N-well type pixel while the second structure is an isolated P-well type pixel. Both structures were fabricated and measurement results are presented in this paper.

A 96×96 1V ultra-low power CMOS image sensor for biomedical application

An ultra-low power CMOS image sensor is designed for endomicroscope applications. The chip will be fabricated through Global Foundries 0.18μm standard CMOS process with 1V power supply. The total power consumption is 6μW for 96×96 array with 5fps frame rate, where global amplifier consumes 3.3 μW, 10-bit SAR ADC consumes 900nW at 50kS/s, and on-chip digital processing further reduces IO power consumption down to 1.6μW.