Suat U. Ay

Optically programmable gate array

The Optically Programmable Gate Array (OPGA), an optical version of a conventional FPGA, benefits from a direct parallel interface between an optical memory and a logic circuit. The OPGA utilizes a holographic memory accessed by an array of VCSELs to program its logic. An active pixel sensor array incorporated into the OPGA chip makes it possible to optically address the logic in a very short time allowing for rapid dynamic reconfiguration. Combining spatial and shift multiplexing to store the configuration pages in the memory, the OPGA module can be made compact. The reconfiguration capability of the OPGA can be applied to solve more efficiently problems in pattern recognition and database search.

Optically reconfigurable processors

Reconfigurable processors bring a new computational paradigm where the processor modifies its structure to suit a given application, rather than having to modify the application to fit the device. The Optically Programmable Gate Array, an enhanced version of a conventional FPGA, utilizes a holographic memory accessed by an array of VCSELs to program its logic. Combining spatial and shift multipexing to store the configuration pages in the memory, the OPGA module is very compact and has extremely short configuration time allowing for dynamic reconfiguration. The reconfiguration capability of the OPGA can be applied to solve more efficiently problems in pattern recognition and digit classification.

Supply boosting technique for designing very low-voltage mixed-signal circuits in standard CMOS

This paper presents a technique called supply boosting for designing sub-1V analog/mixed-signal circuits. Supply boosting technique (SBT) is suitable for sub-micron CMOS processes containing MOSFET transistors with threshold voltages comparable to the supply voltage. SBT is based on the idea that if current consumption of the circuit block is very low, in the order of nanoamper, supply voltage could be boosted locally to higher levels during a period that the processing of input signals is done. This technique is very suitable for very-low power clocked and continuous time circuits such as level shifters, operational amplifiers, and comparators. Design of a 10-bit supply boosted (SB) SAR ADC is presented as an example of the technique. SB-SAR ADC simulated using 0.5µm CMOS process that has high-VT NMOS and PMOS devices. Simulations show that the SB-SAR ADC achieves 0.24pJ/conv-step figure of merit (FOM) when operating ADC at 10KS/sec and 1.2V supply.

A CMOS Energy Harvesting and Imaging (EHI) Active Pixel Sensor (APS) Imager for Retinal Prosthesis

A CMOS image sensor capable of imaging and energy harvesting on same focal plane is presented for retinal prosthesis. The energy harvesting and imaging (EHI) active pixel sensor (APS) imager was designed, fabricated, and tested in a standard 0.5 μm CMOS process. It has 54 × 50 array of 21 × 21 μm2 EHI pixels, 10-bit supply boosted (SB) SAR ADC, and charge pump circuits consuming only 14.25 μW from 1.2 V and running at 7.4 frames per second. The supply boosting technique (SBT) is used in an analog signal chain of the EHI imager. Harvested solar energy on focal plane is stored on an off-chip capacitor with the help of a charge pump circuit with better than 70% efficiency. Energy harvesting efficiency of the EHI pixel was measured at different light levels. It was 9.4% while producing 0.41 V open circuit voltage. The EHI imager delivers 3.35 μW of power was delivered to a resistive load at maximum power point operation. The measured pixel array figure of merit (FoM) was 1.32 pW/frame/pixel while imager figure of merit (iFoM) including whole chip power consumption was 696 fJ/pixel/code for the EHI imager.

Hearing with bionic ears [cochlear implant devices]

According to speech perception-rate data continuous interleaved sampling (CIS) and spectral maxima sound processor (SMSP) techniques are, and probably will be, the best speech processing strategies for multichannel electrode cochlear implant devices. From packaging and power-consumption viewpoints, todays speech processing systems are very big and are, therefore, worn on the body and consume large electric power. Next-generation cochlear implant devices would be more compact, low-power products that would be worn behind or in the ear. It is clear that mixed-signal, high-density, and low-power design techniques are required to satisfy compactness, as well as low-power consumption features to realize intelligent speech sensation for the implantees. The especially critical design consideration of power supply lifetime and efficiency might be increased by using new promising technologies like microelectromechanical systems (MEMS).

A 1.32pW/frame•pixel 1.2V CMOS energy-harvesting and imaging (EHI) APS imager

Recent advances in video sensor networks and implantable biomedical devices — e.g. retinal prostheses [1]-necessitate very low-voltage, low-leakage, and energy-efficient image sensors that preferably produce their own power from ambient sources. A natural energy source for an image sensor that produces video images from impinging “sufficient” amount of light energy is the light itself. This in mind, a CMOS image sensor that can both produce power from light and capture video images on same focal plane is developed. The CMOS energy harvesting and imaging (EHI) active pixel sensor (APS) is incorporated in a 54×50 array along with low-power supporting electronics. It is designed in a mature 0.5μm 2P3M CMOS process that has only high-Vt transistors.

An Ultra-Low Power CMOS Image Sensor with On-Chip Energy Harvesting and Power Management Capability

An ultra-low power CMOS image sensor with on-chip energy harvesting and power management capability is introduced in this paper. The photodiode pixel array can not only capture images but also harvest solar energy. As such, the CMOS image sensor chip is able to switch between imaging and harvesting modes towards self-power operation. Moreover, an on-chip maximum power point tracking (MPPT)-based power management system (PMS) is designed for the dual-mode image sensor to further improve the energy efficiency. A new isolated P-well energy harvesting and imaging (EHI) pixel with very high fill factor is introduced. Several ultra-low power design techniques such as reset and select boosting techniques have been utilized to maintain a wide pixel dynamic range. The chip was designed and fabricated in a 1.8 V, 1P6M 0.18 µm CMOS process. Total power consumption of the imager is 6.53 µW for a 96 × 96 pixel array with 1 V supply and 5 fps frame rate. Up to 30 μW of power could be generated by the new EHI pixels. The PMS is capable of providing 3× the power required during imaging mode with 50% efficiency allowing energy autonomous operation with a 72.5% duty cycle.

An Ultra-Low Power Energy Harvesting and Imaging (EHI) Type CMOS APS Imager With Self-Power Capability

A novel ultra-low power energy harvesting and imaging (EHI) type CMOS active pixel sensor (APS) imager with self-power capability is presented. The proposed EHI type CMOS APS pixel harvests one order of magnitude higher power than that of the other pixel technologies reported in the literature. It produces 46 μW of power under 57 klux illumination. The EHI imager presented has decoupled imaging and harvesting operations such that imaging related circuits are turned off while energy is harvested, and vice versa. The imager can operate on 1 V supply voltage consuming as low as 800 nW while capturing 1 frame per second (fps). Measured minimum full-chip imager FoM is 148 pJ/frame*pixel while capturing 21.2 fps. The imager contains a 64 × 45 array of 18 μm×18 μm EHI pixels. It is manufactured in a standard 2P4M/3.3 V 0.35 μm CMOS process. Ultra-low power operation is achieved by developing new imaging electronics including current reference generator, readout circuits, and SAR type, 8-bit, analog-to digital converter (ADC). A new polarity inverting charge pump circuit was developed for managing the energy harvested by the new energy harvesting pixels on the focal plane.

A nanowatt cascadable delay element for compact power-on-reset (POR) circuits

A cascadable power-on-reset (POR) delay element consuming nanowatt of peak power was developed to be used in very compact power-on-reset pulse generator (POR-PG) circuits. Operation principles and features of the POR delay element were presented in this paper. The delay element was designed, and fabricated in a 0.5µm 2P3M CMOS process. It was determined from simulation as well as measurement results that the delay element works wide supply voltage ranges between 1.8 volt and 5 volt and supply voltage rise times between 100nsec and 1msec allowing wide dynamic range POR-PG circuits. It also has very small silicon footprint. Layout size of a single POR delay element was 35µm x 55µm in 0.5µm CMOS process.

Photodiode Peripheral Utilization Effect on CMOS APS Pixel Performance

A photodiode (PD)-type CMOS active pixel sensor (APS) pixel is comprised of a reverse-biased p-n-junction diode (PD) for photon conversion and charge storage, and a number of MOS transistors. Junction capacitance of the PD has two major components; bottom plate (area) and side wall (periphery). Both play important roles in the electro-optical performance of PD-APS pixels. This paper reports PD peripheral junction utilization effects on the pixels electro-optical performance, full-well capacity and spectral response for an 18times 18 mum CMOS PD-APS pixel were improved by opening multiple circular holes in the PD diffusion layer. A prototype CMOS APS imager was designed, fabricated, and tested in 0.5-mum, 5 V, 2P3M CMOS process, containing a 424 times 424 pixel array with smaller sub-arrays for multiple pixel designs. Four test pixels with 7, 11, 14, and 17 circular, 1.6-mum-diameter holes were placed on one pixel array, with one control pixel for reference. Pixel characteristics, dark current, PD capacitance, quantum efficiency, sensitivity, and pixel full-well capacity were measured. It was found that increased PD junction peripheral would potentially help to improve total capacitance of the PD, with the expense of higher dark current. We also found that increased PD peripheral capacitance improves spectral response up to 12% of the PD-APS pixel, especially at short wavelengths.