Ismat Hijazin

Adaptive gain sliding mode observer for state of charge estimation based on combined battery equivalent circuit model in electric vehicles

An adaptive gain sliding mode observer (AGSMO) for battery state of charge (SOC) estimation based on a combined battery equivalent circuit model (CBECM) is presented. The errors convergences of the AGSMO for the SOC estimation are proved by Lyapunov stability theory. The AGSMO has a capability of compensating modeling errors caused by the parameters variation of the CBECM and minimizing chattering level in SOC estimation. The lithium-polymer battery (LiPB) is used to conduct experiments for extracting the parameters of the CBECM and verifying the effectiveness of the proposed AGSMO for the SOC estimation.

Compact FPGA implementation of PRESENT with Boolean S-Box

Ever since the conception of the ideology known as the Internet of Things (IoT), our world is slowly approaching the brink of mankinds next technological revolution. The realization of IoT requires an enormous amount of sensor nodes to acquire inputs from the connected objects. Due to the lightweight nature of these sensors, constraints emerge in the form of limited power supply and area for the implementation of information security mechanism. To ensure security in the data transmitted by these sensors, lightweight cryptographic solutions are required. In this work, our goal is to implement a compact PRESENT cipher onto a Field Programmable Gate Array (FPGA) platform. Our proposed design uses an 8-bit datapath to reduce hardware size. Instead of a traditional look-up table (LUT) based S-Box, we have implemented a Boolean S-Box through Karnaugh mapping. Further factorization is also done to reduce the size of the Boolean S-Box. As a result, we have achieved the smallest FPGA implementation of the PRESENT cipher to date, requiring only 62 slices on the Virtex-5 XC5VLX50 platform. Our design also features a respectable throughput of 51.32 Mbps at the maximum frequency of 236.574 MHz.

A tree search algorithm for low multiplicative complexity logic design

Abstract Low multiplicative complexity logic design is a useful heuristic to achieve low gate count implementation of logic circuit. In this work, we propose a deterministic approach based on the currently known lower and upper bounds of multiplicative complexity for logic minimization problems with not more than five inputs. The proposed tree search algorithm achieves circuit minimization through decomposition of Positive Polarity Reed–Muller expressions. This approach allows low multiplicative complexity logic design to be executed without the consistency issue associated with the randomized approach in the original algorithm. Experimental results show over 85% improvement in computation time compared to solving the same problems using the previous randomized approach. We also demonstrate that the quality of results produce by the proposed algorithm is comparable, and in some cases, better than the results reported in previous works using the same heuristic.

A novel approach to low multiplicative complexity logic design

Logic optimization over the logic basis (AND, XOR, NOT) has received increased attention in recent works due to the potential in low gate count logic circuit implementation. Previous logic minimization heuristic in this logic basis involved randomized selection processes and thus exhibits uncontrolled variations in the results produced and algorithm execution time. In this work, we demonstrate a novel approach to the same problem using Positive Polarity Reed-Muller factorization. The proposed algorithm eliminates the reliance on randomness and produces all optimal solutions obtainable through the factorization method. This enables the application of different selection criteria post-optimization to maximize circuit sharing between functions. The proposed algorithm is aimed towards optimizing the S-boxes of lightweight cryptographic schemes.

A New Lightweight and High Fault Tolerance Sobel Edge Detection Using Stochastic Computing

A new Stochastic Computing (SC) circuit design paradigm for image processing system is presented in this work. Two improved SC computational functions are derived, which are namely the stochastic scaled addition and stochastic absolute value of difference. Data correlation is also incorporated in the design for effective circuit size reduction without imposing accuracy degradation in the hardware implementations. The proposed SC functions are next employed to design the new and lightweight Sobel edge detection. Experimental results obtained from detailed test analysis have proven that new implementation has satisfactory accuracy level and higher fault tolerance capability in comparison with their conventional counterparts. The works proposed are also implemented on an Altera Cyclone V 5CGXFC7D6F31C6 FPGA for hardware complexity evaluation.

Compact and short critical path finite field inverter for cryptographic S-box

A substitution box (S-box) plays a crucial role in symmetric key cryptography with block ciphers, such as those found in the Data Encryption Standard (DES) and the Advanced Encryption Standard (AES). It serves as the predominant component in most block ciphers, of which the computational complexity impacts the security of the ciphers directly. In essence, a S-box performs a non-linear transformation of the input data block through a finite field inversion, which is incidentally the most expensive operation in digital computation of finite field arithmetic. Consequently, its computational cost will also increase the overall hardware requirements and in turn, decrease the overall performance of the ciphers. With the emergence of Internet of Things (IoT), the need for highly secured yet lightweight implementation protocols is becoming increasingly more observable. In this paper, we propose a new finite field inverter over GF(28) with a significant area cost saving, achieved through direct computation and followed by algebraic factorization and common sub-expression elimination (CSE). The proposed inverter could be deployed into AES cipher on highly area-constrained digital platforms.

Impact of DFIG wind turbines on transient stability of power systems — A review

With the increasing wind power penetration, the wind farms are directly influencing the power systems. The majority of wind farms are using variable speed wind turbines equipped with doubly-fed induction generators (DFIG) due to their advantages over other wind turbine generators. Therefore, the analysis of wind power dynamics with the DFIG wind turbines has become a very important research issue, especially during transient faults. This paper deals with investigating the current research issues in this area, research gaps and limitations in previous works to gestate future research options.