Ming Ming Wong

Construction of Optimum Composite Field Architecture for Compact High-Throughput AES S-Boxes

In this work, we derive three novel composite field arithmetic (CFA) Advanced Encryption Standard (AES) S-boxes of the field GF(((22)2)2). The best construction is selected after a sequence of algorithmic and architectural optimization processes. Furthermore, for each composite field constructions, there exists eight possible isomorphic mappings. Therefore, after the exploitation of a new common subexpression elimination algorithm, the isomorphic mapping that results in the minimal implementation area cost is chosen. High throughput hardware implementations of our proposed CFA AES S-boxes are reported towards the end of this paper. Through the exploitation of both algebraic normal form and seven stages fine-grained pipelining, our best case achieves a throughput 3.49 Gbps on a Cyclone II EP2C5T144C6 field-programmable gate array.

Composite field GF(((22)2)2) Advanced Encryption Standard (AES) S-box with algebraic normal form representation in the subfield inversion

In this study, the authors categorise all of the feasible constructions for the composite Galois field GF(((2 2 ) 2 ) 2 ) Advanced Encryption Standard (AES) S-box into four main architectures by their field representations and their algebraic properties. For each of the categories, a new optimisation scheme which exploits algebraic normal form representation followed by a sub-structure sharing optimisation is presented. This is performed by converting the subfield GF((2 2 ) 2 ) inversion into several logical expressions, which will be in turn reduced using a common sub-expression elimination algorithm. The authors show that this technique can effectively reduce the total area gate count as well as the critical path gate count in composite field AES S-boxes. The resulting architecture that achieves maximum reduction in both total area coverage and critical path gate count is found and reported. The hardware implementations of the authors proposed AES S-boxes, along with their performance and cost are presented and discussed.

Compact and low power AES block cipher using lightweight key expansion mechanism and optimal number of S-Boxes

In the past decade, we observed the trend of technological advancement towards the field of portable electronics. As electronic devices shrink in size, constraints emerge in the form of limited power supply and area for the implementation of information security mechanisms. In this work, our goal is to produce a complete AES block cipher for data encryption and perform optimization in terms of power and size. Unlike the common approach of optimizing the circuitry of the expensive AES S-Box, this work contributes by proposing a compact key expansion mechanism to reduce hardware requirement and deducing the optimal number of S-Boxes to be used in an AES block cipher to achieve the desired performance. In addition, we optimized the design using a series of methodologies which include: (1) implementing the optimized AES S-Box proposed by Wong et al. [2], (2) reducing the number of pipeline registers, and (3) applying input bus sharing. As a result, we achieved three optimized configurations which employ different number of S-Boxes in their architectures. Our best architecture in terms of size and power consumption has a total logic element count of 1818, a total power dissipation of 122.40mW, and a throughput of 198.77Mbps. The design is implemented on a Cyclone II EP2C20F484C7 field-programmable gate array (FPGA).

Compact FPGA implementation of PRESENT with Boolean S-Box

Ever since the conception of the ideology known as the Internet of Things (IoT), our world is slowly approaching the brink of mankinds next technological revolution. The realization of IoT requires an enormous amount of sensor nodes to acquire inputs from the connected objects. Due to the lightweight nature of these sensors, constraints emerge in the form of limited power supply and area for the implementation of information security mechanism. To ensure security in the data transmitted by these sensors, lightweight cryptographic solutions are required. In this work, our goal is to implement a compact PRESENT cipher onto a Field Programmable Gate Array (FPGA) platform. Our proposed design uses an 8-bit datapath to reduce hardware size. Instead of a traditional look-up table (LUT) based S-Box, we have implemented a Boolean S-Box through Karnaugh mapping. Further factorization is also done to reduce the size of the Boolean S-Box. As a result, we have achieved the smallest FPGA implementation of the PRESENT cipher to date, requiring only 62 slices on the Virtex-5 XC5VLX50 platform. Our design also features a respectable throughput of 51.32 Mbps at the maximum frequency of 236.574 MHz.

Composite field GF(((2 2 ) 2 ) 2 ) AES S-Box with direct computation in GF(2 4 ) inversion

Composite field arithmetic (CFA) has been widely used in designing combinatorial logic circuits for the S-Box function in the Advanced Encryption Standard (AES) in order to mitigate the performance bottleneck in VLSI implementation. In this work, we first categorize all of the possible composite field AES S-box constructions into four main architectures based on their field representations and the chosen algebraic properties. Each category is then investigated thoroughly. Next, we show that by computing the F(24) inversion directly in the composite field F(((22)2)2), we can further reduce the total area gate count as well as the critical path gate count. The architecture that leads to the maximum reduction in both total area coverage and critical path gate count through the exploitation of direct computation in F(24) inversion is found and reported. Our best architecture has a total area gate count of 35 AND gates and 117 XOR gates and critical path gate count of 3 AND gates and 20 XOR gates.

New lightweight AES S-box using LFSR

The paper presents a new design approach for AES SubBytes transformation (S-box) by using the Linear Feedback Shift Register (LFSR). In the past, composite field arithmetic (CFA) is commonly deployed as it effectively produces lightweight and pure combinational architecture. Unfortunately, the downside of this methodology is that the resultant circuitry is complex in nature, which leads to long critical path and high power consumption. On the other hand, the proposed solution in this work is relatively simple which comprised of a pair of identical LFSRs, two comparators and a multiplexer. LFRS is employed to replace the CFA in performing the multiplicative inversion over GF(28). The resultant architecture is proven to consume less hardware space and having low routing complexity, hence suitable for lightweight embedded devices.

A tree search algorithm for low multiplicative complexity logic design

Abstract Low multiplicative complexity logic design is a useful heuristic to achieve low gate count implementation of logic circuit. In this work, we propose a deterministic approach based on the currently known lower and upper bounds of multiplicative complexity for logic minimization problems with not more than five inputs. The proposed tree search algorithm achieves circuit minimization through decomposition of Positive Polarity Reed–Muller expressions. This approach allows low multiplicative complexity logic design to be executed without the consistency issue associated with the randomized approach in the original algorithm. Experimental results show over 85% improvement in computation time compared to solving the same problems using the previous randomized approach. We also demonstrate that the quality of results produce by the proposed algorithm is comparable, and in some cases, better than the results reported in previous works using the same heuristic.

A novel approach to low multiplicative complexity logic design

Logic optimization over the logic basis (AND, XOR, NOT) has received increased attention in recent works due to the potential in low gate count logic circuit implementation. Previous logic minimization heuristic in this logic basis involved randomized selection processes and thus exhibits uncontrolled variations in the results produced and algorithm execution time. In this work, we demonstrate a novel approach to the same problem using Positive Polarity Reed-Muller factorization. The proposed algorithm eliminates the reliance on randomness and produces all optimal solutions obtainable through the factorization method. This enables the application of different selection criteria post-optimization to maximize circuit sharing between functions. The proposed algorithm is aimed towards optimizing the S-boxes of lightweight cryptographic schemes.

A New Lightweight and High Fault Tolerance Sobel Edge Detection Using Stochastic Computing

A new Stochastic Computing (SC) circuit design paradigm for image processing system is presented in this work. Two improved SC computational functions are derived, which are namely the stochastic scaled addition and stochastic absolute value of difference. Data correlation is also incorporated in the design for effective circuit size reduction without imposing accuracy degradation in the hardware implementations. The proposed SC functions are next employed to design the new and lightweight Sobel edge detection. Experimental results obtained from detailed test analysis have proven that new implementation has satisfactory accuracy level and higher fault tolerance capability in comparison with their conventional counterparts. The works proposed are also implemented on an Altera Cyclone V 5CGXFC7D6F31C6 FPGA for hardware complexity evaluation.

Compact and short critical path finite field inverter for cryptographic S-box

A substitution box (S-box) plays a crucial role in symmetric key cryptography with block ciphers, such as those found in the Data Encryption Standard (DES) and the Advanced Encryption Standard (AES). It serves as the predominant component in most block ciphers, of which the computational complexity impacts the security of the ciphers directly. In essence, a S-box performs a non-linear transformation of the input data block through a finite field inversion, which is incidentally the most expensive operation in digital computation of finite field arithmetic. Consequently, its computational cost will also increase the overall hardware requirements and in turn, decrease the overall performance of the ciphers. With the emergence of Internet of Things (IoT), the need for highly secured yet lightweight implementation protocols is becoming increasingly more observable. In this paper, we propose a new finite field inverter over GF(28) with a significant area cost saving, achieved through direct computation and followed by algebraic factorization and common sub-expression elimination (CSE). The proposed inverter could be deployed into AES cipher on highly area-constrained digital platforms.