Itai Jaeger

X-Gen: a random test-case generator for systems and SoCs

We present X-Gen, a model-based test-case generator designed for systems and systems on a chip (SoC). X-Gen provides a framework and a set of building blocks for system-level test-case generation. At the core of this framework lies a system model, which consists of component types, their configuration, and the interactions between them. Building blocks include commonly used concepts such as memories, registers, and address translation mechanisms. Once a system is modeled, X-Gen provides a rich language for describing test cases. Through this language, users can specify requests that cover the full spectrum between highly directed tests to completely random ones. X-Gen is currently in preliminary use at IBM for the verification of two different designs - a high-end multi-processor server and a state-of-the-art SoC.

Addressing Test Generation Challenges for Configurable Processor Verification

Having only recently entered the mainstream, configurable processor technology already provides practical automated hardware design. In this paper, we address the challenges of verifying these software-constructed hardware artifacts and show that sophisticated automation is mandatory. We describe how a model-based test generation technology was integrated into the verification flow of a configurable processor design. We report on experiments with two complex verification tasks. In both experiments, the model-based technology has achieved much higher coverage than standard verification tools and required considerably fewer engineering resources. We conclude that processor-oriented test generation technology addresses well the challenges of verifying automated hardware design

Path-Based system level stimuli generation

Over the last few years, there has been increasing emphasis on integrating ready-made components (IP, cores) into complex System on a Chip (SoC) designs. The verification of such designs poses new challenges. At the heart of these challenges lies the requirement to verify the integration of several previously designed components in a relatively short time. Simulation-based methods are the main verification vehicle used for system-level functional verification of SoC designs; therefore, stimuli generation plays an important role in this field. Our work offers a solution for efficiently dealing with the verification of systems with multiple configurations and derivative systems, a common challenge in the context of system verification. We present a generation scheme in which the system behavior is defined using a combination of transaction-based modeling, local component behavior, and the topology of the system. We show how this approach allows the implementation of the verification plan using high level constructs and promotes the reuse of verification IP between systems. The ideas described below were implemented as part of X-Gen, a system-level test-case generator developed and used in IBM.