Allon Adir

A unified methodology for pre-silicon verification and post-silicon validation

The growing importance of post-silicon validation in ensuring functional correctness of high-end designs increases the need for synergy between the pre-silicon verification and post-silicon validation. We propose a unified functional verification methodology for the pre- and post-silicon domains. This methodology is based on a common verification plan and similar languages for test-templates and coverage models. Implementation of the methodology requires a user-directable stimuli generation tool for the post-silicon domain. We analyze the requirements for such a tool and the differences between it and its pre-silicon counterpart. Based on these requirements, we implemented a tool called Threadmill and used it in the verification of the IBM POWER7 processor chip with encouraging results.

Threadmill: a post-silicon exerciser for multi-threaded processors

Post-silicon validation poses unique challenges that bring-up tools must face, such as the lack of observability into the design, the typical instability of silicon bring-up platforms and the absence of supporting software (like an OS or debuggers). These challenges and the need to reach an optimal utilization of the expensive but very fast silicon platforms lead to unique design considerations - like the need to keep the tool simple and to perform most of its operation on platform without interaction with the environment. In this paper we describe a variety of novel techniques optimized for the unique characteristics of the silicon platform. These techniques are implemented in Threadmill - a bare-metal exerciser targeting multi-threaded processors. Threadmill was used in the verification of the POWER7 processor with encouraging results

Generating concurrent test-programs with collisions for multi-processor verification

We discuss collisions that are of interest to multiprocessor verification. Collisions occur when different processes access a shared resource. We investigate how the results of such collisions can be presented in test programs and suggest implementations for automatically generating such tests and predicting the results of collision scenarios. Most of the ideas presented are the result of years of experience with two multi-processor test generators from IBM (Genie and Genesys-Pro) which are also briefly presented.

Reaching coverage closure in post-silicon validation

Obtaining coverage information in post-silicon validation is a difficult task. Adding coverage monitors to the silicon is costly in terms of timing, power, and area, and thus even if feasible, is limited to a small number of coverage monitors. We propose a new method for reaching coverage closure in post-silicon validation. The method is based on executing the post-silicon exercisers on a pre-silicon acceleration platform, collecting coverage information from these runs, and harvesting important test templates based on their coverage. This method was used in the verification of IBMs POWER7 processor. It contributed to the overall high-quality verification of the processor, and specifically to the post-silicon validation and bring-up.

Piparazzi: a test program generator for micro-architecture flow verification

Because of their complexity, modern microprocessors need new tools that generate tests for micro-architectural events. Piparazzi is a test generator, developed at IBM, that generates (architectural) test programs for microarchitectural events. Piparazzi uses a declarative model of the micro-architecture and the users definition of the required event to create an instance of a Constraint Satisfaction Problem (CSP). It then uses a dedicated CSP solver to generate a test program that covers the specific event. We show how Piparazzi yields significant improvements in covering micro-architectural events, by describing its technology and by exhibiting experimental results. Piparazzi has already been successful in finding both functional and performance bugs that could only be discovered using an exact micro-architectural model of the processor.

Leveraging pre-silicon verification resources for the post-silicon validation of the IBM POWER7 processor

The growing importance of post-silicon validation in ensuring functional correctness of high-end designs has increased the need for synergy between the pre-silicon verification and post-silicon validation. This synergy starts with a common verification plan. It continues with common verification goals and shared tools and techniques. This paper describes our experience in improving this synergy in the pre- and post-silicon verification of IBMs POWER7 processor chip and by leveraging pre-silicon methodologies and techniques in the post-silicon validation of the chip.

DeepTrans - a model-based approach to functional verification of address translation mechanisms

We present a new test case generation technology, specifically targeted at verifying systems that include address translation mechanisms. The ever-growing demand for performance makes these mechanisms more complex, thereby increasing the risk of bugs and increasing the need for such technology. DeepTrans is a package that provides model-based test generation capabilities to verify translation mechanisms based on a modeling language. The modeling language includes constructs for describing the address translation process, commonly used translation resources, and architecture rules related to translation. DeepTrans is currently used by two different IBM test generators.

Verification of Transactional Memory in POWER8

Transactional memory is a promising mechanism for synchronizing concurrent programs that eliminates locks at the expense of hardware complexity. Transactional memory is a hard feature to verify. First, transactions comprise several instructions that must be observed as a single global atomic operation. In addition, there are many reasons a transaction can fail. This results in a high level of non-determinism which must be tamed by the verification methodology. This paper describes the innovation that was applied to tools and methodology in pre-silicon simulation, acceleration and post-silicon in order to verify transactional memory in the IBM POWER8 processor core.

Advances in simultaneous multithreading testcase generation methods

Many modern microprocessor architectures utilize simultaneous multithreading (SMT) for increased performance. This trend is exemplified in IBMs Power series of high-end microprocessors which steadily increased the number of threads in a system in its POWER5, POWER6 and POWER7 designs. In this paper we discuss the steady increase in functional verification complexity introduced by each of these designs and the corresponding improvements to SMT verification methods that were necessary in order to cope with the growing verification challenge. We review three different verification technologies which were specifically developed to target SMT aspects of processor designs, and compare their relative advantages and drawbacks. Our focus is on the novel Thread Irritation technique - we demonstrate its effectiveness in finding high quality SMT bugs early in the verification cycle, and show how it was adopted to the post-silicon platform.

Adaptive test program generation: planning for the unplanned

Simulation of automatically-generated test programs is the primary means for verifying complex hardware designs and random test program generators therefore play a major role in the verification process of micro-processors. The input for a test program generator is typically an abstract specification-a template-of the tests to be generated. Due to randomness, generators often encounter situations that were not anticipated when the test specification was written. We introduce the concept of adaptive test program generation, which is designed to handle these unforeseen situations. We propose a technique that defines unexpected events together with their alternative program specifications. When an event is detected, its corresponding alternative specification is injected into the test program.