Itsuo Takanami

On fault injection approaches for fault tolerance of feedforward neural networks

To make a neural network fault-tolerant, Tan et al. proposed a learning algorithm which injects intentionally the snapping of a wire one by one into a network (1992, 1992, 1993). This paper proposes a learning algorithm that injects intentionally stuck-at faults to neurons. Then by computer simulations, we investigate the recognition rate in terms of the number of snapping faults and reliabilities of lines and the learning cycle. The results show that our method is more efficient and useful than the method of Tan et al. Furthermore, we investigate the internal structure in terms of ditribution of correlations between input values of a output neuron for the respective learning methods and show that there is a significant difference of the distributions among the methods.

A fault-value injection approach for multiple-weight-fault tolerance of MNNs

Many studies of methods for making multilayer neural nets (MNN) fault-tolerant by injecting intentionally the snapping of a link or a noise into links in the learning process have considered fault-tolerance to link snapping. We consider fault-tolerance to the weight fault, which includes link snapping as a special case. We take a pattern recognition problem as an example. To make an MNN fault-tolerant to any single or double weight faults in a certain interval or range, we inject intentionally two extreme points of a single or double fault-values in an interval or a range during learning. By simulation, we investigate how much MNN becomes fault-tolerant to the weight faults depending on the injected ones. The degree of fault-tolerance for a n-multiple weight fault is estimated by the number of essential multiple links. An interesting result that if only two faults of the extreme points in the interval are injected, the number of the essential links becomes zero for single faults of all the weights in the interval is obtained. This means that MNN becomes fault-tolerant to any single weight faults in the interval. Expecting that the similar result for double faults will be obtained, we inject two extreme points in two-dimensional range. As expected, the number of 2-multiple essential links has become zero in the range. This means that MNN becomes fault-tolerant to any double weight faults in the range. Finally, we analyse the internal structure of MNN by the distribution of covariance between any two inputs of a neuron in the output layer.

A neural algorithm for reconstructing mesh-connected processor arrays using single-track switches

To overcome faults in mesh-connected processor arrays, a number of reconfiguration schemes have been studied in the literature. One of them, the mesh-connected processor arrays model based on single-track switches, has been proposed in. The model has the advantage of its inherent simplicity of the routing hardware. So far, some algorithms have been proposed to solve the problem of reconfiguration for this model. For example, a polynomial time algorithm has been presented. However, it needs global information on fault distribution and it seems to be a troublesome job to implement the algorithm even by software while it may be impossible to implement it by hardware. In this paper, using a Hopfield-type neural network model, we present an algorithm for reconstructing the mesh-connected processor arrays using single-track switches and show its effectiveness by computer simulation. Furthermore, we present a hardware implementation of the neural algorithm by which a self-repair system can be realized.

A built-in self-reconfigurable scheme for 3D mesh arrays

We propose a model for fault tolerant 3D processor arrays using one-and-half track switches. Spare processors are laid on the two opposite surfaces of the 3D array. The fault compensation process is performed by shifting processors on a continuous straight line from a faulty processor to a spare on the surfaces. Two opposite directions are allowed for compensation paths only which they are not in the near-miss relation. Then, switches with only 4 states are needed to preserve the 3D mesh topology after compensating faults. We give an algorithm in a convenient form for reconfiguring by hardware the 3D mesh arrays with faults and show the survival rates and the probabilities of them by computer simulation. The probabilities are compared with those of the case using double tracks which have no restriction of the near-miss relation. The algorithm can reconfigure the 3D mesh arrays in polynomial time. Finally, we design a logical circuit for hardware realization of the algorithm. This will be able to make us build such a built-in self-reconfigurable 3D mesh array that the reconfiguration can be done very quickly.

Built-in self-reconfiguring systems for fault tolerant mesh-connected processor arrays by direct spare replacement

Gives built-in self-reconfiguring systems for mesh-connected processor arrays with faulty processors (PEs) which are directly replaced by spare PEs on two orthogonal lines at the edges of the arrays or on the diagonal line of the arrays. To do so, using a Hopfield-type neural network model, we present an algorithm for reconstructing the arrays mentioned above and show its efficiency of reconstruction by computer simulations. Next, we show how the algorithm can be realized by a digital neural circuit. The circuit can be embedded in a target processor array to reconstruct quickly the array with faulty PEs without the aid of a host computer. This implies that the proposed systems are effective in enhancing the run-time reliabilities of the processor arrays.

Reconfiguration of 1 1/2 track-switch mesh-arrays with PE and bus faults

The mesh-connected processor array model using 1 1/2 track-switches has an advantage of its inherent simplicity of the routing hardware. In this paper, for the model, we investigate its fault tolerant ability for simultaneous processor element (PE) and bus faults. First, we discuss how interconnections are restructured, avoiding faulty PE and buses. Then, we present a neural algorithm for reconfiguration, using a Hopfield-type neural network model. We show the influence of bus faults on the reliabilities of arrays by simulation. The proposed neural algorithm has an advantage that the computation time for reconstruction is so small. Furthermore, the algorithm has a potentiality that a built-in self-reconfigurable system may be realized by implementing the algorithm by hardware in a less complicated way.

Reconfigurable architectures for mesh-arrays with PE and link faults

We propose reconstruction architectures for mesh-arrays with link faults as well as processor element (PE) faults. First, we explain a method for compensating link faults and give a compensation algorithm for the case where no PE is faulty. Then, the reliabilities of the proposed interconnection networks are obtained by computer simulation and are compared with that of the network with doubly duplicated links. Next, we show how PE faults are compensated using the proposed network. It is seen that when no link is faulty, the ability of compensation is greater than that of the reconstruction strategy using single-track switches but is less than that of the strategy allowing the horizontal or vertical compensation paths to the spares on the boundary of mesh-arrays to cross. Finally considering that the proposed architectures have several routes to connect healthy PEs with each other, avoiding faulty PE, we propose an algorithm for coping with simultaneous faults of PEs and interconnection links.

Switching networks and neural algorithms for reconstructing mesh-connected processor arrays with spares on their sides

First, we present switching networks and a reconstruction strategy for mesh-connected processor arrays with linear arrays of spares on their left/right/upper/bottom sides. Each faulty processor is compensated by a spare on any one of left/right/upper/bottom sides. The reconstruction is done by shifting vertically first and then horizontally. Such a new reconstruction strategy leads to the simple and systematic switching operations for the networks. The networks are regular and comparatively simple. The distances between logically adjacent processors after the reconstruction are bounded by a constant. Next, we describe exhaustive algorithms for reconstruction. It seems that efficient ones can not be found. So, using a Hopfield-type neural network model, we present algorithms for the two cases where the linear arrays of spares are on the right and bottom sides, and on the right and left and bottom sides, and show their effectiveness by computer simulation.<<ETX>>

Built-in self-reconfiguring systems for mesh-connected processor arrays with spares on two rows/columns

The author discusses some reconfiguration methods where faulty PEs are compensated for by spare PEs located in two rows/columns in/around a mesh-connected array since they have the advantages that the numbers of spare PEs and the network overheads for reconstructions are relatively small. First, the author discusses how arrangements of spare PEs and network architectures affect the efficiencies of reconfigurations. As arrangements of spare PEs, he considers the cases where either spare linear arrays face each other or are located orthogonally. As replacements of faulty PEs by spare PEs, straight shifts using double or single tracks are considered. Reconfiguration algorithms are given for the proposed methods. The efficiencies of reconfigurations for the methods, that is, the reconfiguration probabilities, are compared with each other. Finally, the author presents built-in self-reconfiguring systems for the proposed methods by hardware. This implies that the proposed methods are effective in enhancing the run-time reliabilities as well as the fabrication-time yields of the processor arrays.

A polynomial time algorithm for reconfiguring the 1 1/2 track-switch model with PE and bus faults

As VLSI technology has developed, the interest in implementing an entire or significant part of a parallel computer system using wafer scale integration is growing. The major problem for the case is the possibility of drastically low yield and/or reliability of the system if there is no strategy for coping with such situations. Various strategies to restructure the faulty physical system into the fault-free target logical system are described in the literature. These restructures are performed using interconnection networks consisting of links and switches. Then the reliabilities of the systems depend on those of PEs and the interconnection networks. However, as far as we know, there are few studies considering the simultaneous faults of PEs and interconnection links. In this paper, by extending the Roychowdhurys (1989) algorithm, we propose a polynomial time algorithm for reconfiguring the 1 1/2 track-switch model compensating for simultaneous PE and bus faults.