Tadayoshi Horita

A Built-in Circuit for Self-Repairing Mesh-Connected Processor Arrays by Direct Spare Replacement

We present a self-repairing circuit for a mesh-connected processor array with faulty processing elements which are directly replaced by spare processing elements on two orthogonal lines at the edges of the array. First, the spare assignment problem is formalized as a matching problem in graph theory. Using the result, we present an algorithm for reconstructing the array in a convenient form for finding the matching by a logical circuit. Second, the logical circuit which exactly realizes the algorithm is given. The circuit can be embedded in a target processor array to reconstruct very quickly the array with faulty processing elements without the aid of a host computer. This implies that the proposed system is effective in enhancing especially the run-time reliability of a processor array.

A built-in self-reconfigurable scheme for 3D mesh arrays

We propose a model for fault tolerant 3D processor arrays using one-and-half track switches. Spare processors are laid on the two opposite surfaces of the 3D array. The fault compensation process is performed by shifting processors on a continuous straight line from a faulty processor to a spare on the surfaces. Two opposite directions are allowed for compensation paths only which they are not in the near-miss relation. Then, switches with only 4 states are needed to preserve the 3D mesh topology after compensating faults. We give an algorithm in a convenient form for reconfiguring by hardware the 3D mesh arrays with faults and show the survival rates and the probabilities of them by computer simulation. The probabilities are compared with those of the case using double tracks which have no restriction of the near-miss relation. The algorithm can reconfigure the 3D mesh arrays in polynomial time. Finally, we design a logical circuit for hardware realization of the algorithm. This will be able to make us build such a built-in self-reconfigurable 3D mesh array that the reconfiguration can be done very quickly.

Learning Algorithms Which Make Multilayer Neural Networks Multiple-Weight-and-Neuron-Fault Tolerant

Two simple but useful methods, called the deep learning methods, for making multilayer neural networks tolerant to multiple link-weight and neuron-output faults, are proposed. The methods make the output errors in learning phase smaller than those in practical use. The abilities of fault-tolerance of the multilayer neural networks in practical use, are analyzed in the relationship between the output errors in learning phase and in practical use. The analytical result shows that the multilayer neural networks have complete (100%) fault-tolerance to multiple weight-and-neuron faults in practical use. The simulation results concerning the rate of successful learnings, the ability of fault-tolerance, and the learning time, are also shown.

A Multiple-Weight-and-Neuron-Fault Tolerant Digital Multilayer Neural Network

This paper introduces an implementation method of multiple weight as well as neuron fault-tolerant multilayer neural networks. Their fault-tolerance is derived from our extended back propagation learning algorithm called the deep learning method. The method can realize a desired weight as well as neuron fault-tolerance in multilayer neural networks where weight values are floating-point and the sigmoid function is used to calculate neuron output values. In this paper, fault-tolerant multilayer neural networks are implemented as digital circuits where weight values are quantized and the step function is used to calculate neuron output values using the deep learning method, the VHDL notation, and the logic design software QuartusII of Altera Inc. The efficiency of our method is shown in terms of fabrication-time cost, hardware size, neural computing time, generalization property, and so on

Multilayer Perceptrons Which Are Tolerant to Multiple Faults and Learnings to Realize Them

We discuss a fault-tolerance of multilayer perceptrons in which input and output learning examples are patterns consisting of 0s and 1s. A type of faults to be dealt with is a multiple neuron and/or weight fault where neurons are in the hidden layer and weights are between the hidden and output layers. We theoretically analyze the condition when a multilayer perceptron is tolerant to multiple neuron and weight faults. According to the analysis, we propose two value injection methods denoted as VIM-WN and VIM-N to make multilayer perceptrons tolerant to all multiple neuron and/or weight faults whose values are in a multi-dimensional interval. In VIM-WN, the extreme values specified by the fault ranges are set to the outputs of the selected neurons and the selected weights of the links at the same time in a learning phase. In VIM-N, the extreme values specified by the fault ranges are set only to the outputs of the selected neurons likewise. First, we present an algorithm based on VIM-WN and prove that a multilayer perceptron which has successfully finished learning by VIM-MN is tolerant to all multiple neuron-and-weight faults whose values are in the interval, under the condition that the multiplicity of the multiple fault is within a certain number specified by faulty neurons and weights. Next, we present them concerning VIM-N likewise. By simulation, we confirm the analytical results for VIM-WN and VIM-N. We also by simulation examine the degrees of fault tolerance concerning multiple neuron-and-weight faults for VIM-N and VIM-W where VIM-W is the method proposed in [1] and show that VIM-N and WIM-W as well as VIM-WN are almost equally effective in coping with multiple neuron-and-weight faults. In addition, we show the data in terms of the learning time, successful rate of learning.

Reconfiguration of 1 1/2 track-switch mesh-arrays with PE and bus faults

The mesh-connected processor array model using 1 1/2 track-switches has an advantage of its inherent simplicity of the routing hardware. In this paper, for the model, we investigate its fault tolerant ability for simultaneous processor element (PE) and bus faults. First, we discuss how interconnections are restructured, avoiding faulty PE and buses. Then, we present a neural algorithm for reconfiguration, using a Hopfield-type neural network model. We show the influence of bus faults on the reliabilities of arrays by simulation. The proposed neural algorithm has an advantage that the computation time for reconstruction is so small. Furthermore, the algorithm has a potentiality that a built-in self-reconfigurable system may be realized by implementing the algorithm by hardware in a less complicated way.

A Built-in Self-repair Circuit for Restructuring Mesh-Connected Processor Arrays by Direct Spare Replacement

We present a digital circuit for restructuring a mesh-connected processor array with faulty processing elements which are directly replaced by spare processing elements located at two orthogonal sides of the array. First, the spare assignment problem is formalized as a matching problem in graph theory. Using the result, we present an algorithm for restructuring the array in a convenient form for finding a matching by a digital circuit. Second, the digital circuit which exactly realizes the algorithm is given. The circuit can be embedded in a target processor array to restructure very quickly the array with faulty processing elements without the aid of a host computer. This implies that the proposed system is effective in not only enhancing the run-time reliability of a processor array but also such an environment that the repair by hand is difficult or a processor array is embedded within a VLSI chip where faulty processor elements cannot be monitored externally through the boundary pins of the chip, and so on. Third, the data about the array reliability considering not only faults in processors but also in that digital circuit are given, and then the effectiveness of our scheme is shown.

An FPGA-Based Multiple-Weight-and-Neuron-Fault Tolerant Digital Multilayer Perceptron (Full Version)

A method to implement a digital multilayer perceptron (DMLP) in an FPGA is proposed, where the DMLP is tolerant to simultaneous weight and neuron faults. It has been shown in [1] that a multilayer perceptron (MLP) which has successfully trained using the deep learning method is tolerant to multiple weight and neuron faults where the weight faults are between the hidden and output layers, and the neuron faults are in the hidden layer. Using this fact, a set of weights in the trained MLP is installed in an FPGA to cope with these faults. Further, the neuron faults in the output layer are detected or corrected using SECDED code. The above process is done as follows. The generator developed by us automatically outputs a VHDL source file which describes the perceptron using a set of weight values in the MLP trained by the deep learning method. The VHDL file obtained is input to the logic design software Quartus II of Altera Inc., and then, implemented in an FPGA. The process is applied to realizing fault-tolerant DMLPs for character recognitions as concrete examples. Then, the perceptrons to be made fault-tolerant and corresponding non-redundant ones not to be made fault-tolerant are compared in terms of not only reliability and fault rate but also hardware size, computing speed and electricity consumption. The data show that the fault rate of the fault-tolerant perceptron can be significantly decreased than that of the corresponding non-redundant one.

An Analysis for Fault-Tolerant 3D Processor Arrays Using 1.5-Track Switches

This paper deals with redundant 3D mesh processor arrays using 1.5-track switches, considering track and switch faults together with processor faults. Four variants are defined based on the distributions of spare PEs, and arrays of three variants have the same PE redundancies among them, but the fabrication-time costs are different. We investigate in detail how the reliability of a total system changes according to the reliabilities of tracks and switches as well as PEs, and show the concrete values of Mt and Ms, when the reliability of array are almost the same even if its variant is changed, and when it is not so, respectively, where Mt and Ms are the ratio of the hardware complexities of a PE and a track, and that of a PE and a contact point of a switch, respectively. Other results which are effective basis for the design of fault-tolerant 3D PE arrays using 1.5-TSs are given.

A system for efficiently self-reconstructing E-1 1/2 track switch torus arrays

A mesh-connected processor array consists of many similar processing elements (PEs), which can be executed in both parallel and pipeline processing. For the implementation of an array of large numbers of processors, it is necessary to consider some fault tolerant issues to enhance the (fabrication-time) yield and the (run-time) reliability. We introduce the E-1 1/2 -TS torus array ray model and apply the EAR method (that is an extended approximate reconfiguration method) to the array. We show that the E-1 1/2 -TS torus arrays with the hardware realization of the EAR algorithm are very efficient at the point of the array yield (or reliability) and suitable for run-time as well as fabrication-time fault-tolerance for mesh or torus connected processor arrays even though an additional logic circuit (about 200 gates per processor) is required.