Iuri Mehr

A 55-mW, 10-bit, 10 Msample/s Nyquist rate CMOS ADC

A low-power 10-bit converter that can sample input frequencies above 100 MHz is presented. The converter consumes 55 mW when sampling at f/sub s/=40 MHz from a 3-V supply, which also includes a bandgap and a reference circuit (70 mW if including digital drivers with a 10-pF load). It exhibits higher than 9.5 effective number of bits for an input frequency at Nyquist (f/sub in/=f/sub s//2=20 MHz). The differential and integral nonlinearity of the converter are within /spl plusmn/0.3 and /spl plusmn/0.75 LSB, respectively, when sampling at 40 MHz, and improve to a 12-bit accuracy level for lower sampling rates. The overall performance is achieved using a pipelined architecture without a dedicated sample/hold amplifier circuit at the input. The converter is implemented in double-poly, triple-metal 0.35-/spl mu/m CMOS technology and occupies an area of 2.6 mm/sup 2/.

A High Dynamic Range CMOS Variable Gain Amplifier for Mobile DTV Tuner

A high dynamic range RF variable gain amplifier (RFVGA) suitable for mobile digital television (DTV) tuners is presented. Variable gain is achieved using a capacitive attenuator and current-steering transconductance (Gm) stages, which provide high linearity with relatively low power consumption. A novel broadband input impedance matching scheme based on resistive shunt-feedback is proposed. This scheme allows the RFVGA to achieve a low noise figure. A gain control technique suitable for CMOS current-steering variable gain amplifiers is described; it features 1 dB per step resolution, independent of process and temperature variations. The chip is fabricated in six-metal 0.18mum CMOS technology and consumes 12.2mA current from 1.8V supply. The RFVGA achieves 16dB maximum gain, 33dB gain control range, a 4.3dB noise figure, and an IIP3 higher than 25dBm

A CMOS continuous-time G/sub m/-C filter for PRML read channel applications at 150 Mb/s and beyond

Design techniques for equiripple phase CMOS continuous-time filters are presented, and their integration within a partial-response maximum likelihood (PRML) disk drive read channel is discussed. A programmable seven-pole two asymmetric zero filter implementation is described based on a new transconductance (G/sub m/) cell. The impact of integrator finite output impedance, excess phase, and other implementation related nonidealities is discussed. A filter tuning circuit that requires an accurate time base but no external components is presented. The filter has a cutoff frequency (f/sub c/) range of 6-43 MHz, where f/sub c/ is the -3 dB point of the magnitude transfer function with the two zeros set to infinity. Also, with finite zeros it is able to provide up to 12 dB of boost which is defined as the maximum value of the magnitude transfer function referred to dc. The group delay ripple stays within /spl plusmn/2% for frequencies below 1.75 f/sub c/. The cutoff frequency exhibits a 650 ppm//spl deg/C temperature dependency and a variation of /spl plusmn/1%/V with the power supply. Total harmonic distortion (THD) values are below -40 dB at twice the nominal operating input voltage (V/sub nominal/=320 mV peak-to-peak differential), and the dynamic range exceeds 60 dB (for a maximum input signal of 640 mV peak-to-peak differential, maximum bandwidth setting, and no boost). Both the filter and a tuning circuit were implemented in a 0.6-/spl mu/m single-poly triple-metal n-well CMOS process. They consume 90 mW from a single 5 V power supply and occupy an area of 0.8 mm/sup 2/.

A 500-MSample/s, 6-bit Nyquist-rate ADC for disk-drive read-channel applications

The analog-to-digital conversion required in most disk drive read channel applications is designed for good dynamic and noise performance over a wide input frequency range. This paper presents a 500MSam- ple/s 6-Bit ADC and its embedded implementation inside a disk drive read channel, using a 0.35µm CMOS single-poly, triple-metal process. The converter achieves better than 5 effective number of bits (ENOB) for input frequencies up to Nyquist frequency (fin= 1/2fs) and sampling frequencies fsup to 400MHz. It also achieves better that 5.6 ENOB for input frequencies up to 1/4fsover process, temperature and power supply variations. At maximum speed (fs= 500MHz) the converter still achieves better than 5 ENOB for input frequencies up to fin= 200MHz. Low frequency performance is characterized by DNL < 0.38LSB and INL < 0.2LSB. The converter consumes 225mW from a 3.3V supply when running at 300MHz and occupies 0.8mm2of chip area.

A 3 V 340 mW 14 b 75 MSPS CMOS ADC with 85 dB SFDR at Nyquist

A 14 b multi-bit ADC with a switched-capacitor pipeline architecture achieves 0.6 LSB DNL and 2 LSB INL without calibration. Typical SNR is 73 dB, while SFDR is >85 dB for input frequency up to Nyquist. The 7.8 mm/sup 2/ ADC in 0.35 μm double-poly triple-metal process operates with a 2.7 V to 3.6 V power supply, and consumes 340 mW at 3 V.

A 375-mW Quadrature Bandpass

A quadrature bandpass DeltaSigma ADC for a multistandard TV tuner achieves a total dynamic range of 90 dB over an 8.5-MHz passband centered on 44 MHz while consuming 375 mW. The fourth-order continuous-time ADC uses active-RC resonators configured in a modified feedforward architecture

\Delta\Sigma

A multipurpose TV tuner front-end implemented in 0.35/spl mu/m BiCMOS technology is presented. It employs a dual-conversion topology and a fully integrated RF automatic gain control loop. The tuner front-end achieves -68dB composite-triple beat (CTB) distortion and a noise figure of 6.8-7.4dB in a 50-870Mhz input frequency range. In addition, the front-end is interfaced with a companion chip, which contains a high dynamic range ADC combined with programmable digital filters to accommodate multi-standard operation.

ADC With 8.5-MHz BW and 90-dB DR at 44 MHz

The analog-to-digital conversion required in most disk drive read channel applications is designed for good dynamic and noise performance over a wide input frequency range. This paper presents a 500MSam- ple/s 6-Bit ADC and its embedded implementation inside a disk drive read channel, using a 0.35µm CMOS single-poly, triple-metal process. The converter achieves better than 5 effective number of bits (ENOB) for input frequencies up to Nyquist frequency (f in = 1/2f s ) and sampling frequencies f s up to 400MHz. It also achieves better that 5.6 ENOB for input frequencies up to 1/4f s over process, temperature and power supply variations. At maximum speed (f s = 500MHz) the converter still achieves better than 5 ENOB for input frequencies up to f in = 200MHz. Low frequency performance is characterized by DNL < 0.38LSB and INL < 0.2LSB. The converter consumes 225mW from a 3.3V supply when running at 300MHz and occupies 0.8mm2of chip area.

A dual-conversion tuner for multi-standard terrestrial and cable reception

The inaccuracies obtained by sampling a dynamic input signal is a major source of error in current-mode circuits. A sampled-data feedback architecture is presented for the design of a high-linearity current sample/hold that uses oversampling to overcome the nonlinearity of internal components. Both system and circuit level considerations are discussed, culminating in the design and implementation of both first- and second-order structures in a 2 /spl mu/m p-well CMOS process. Limited test results show a linearity of up to 69 dB at a sampling rate of 5 MHz. These circuits provide an excellent sampling stage for the realization of a high-resolution current-mode /spl Delta//spl Sigma/ A/D converter in a digital CMOS process.

A 500 msample/s 6&#8211;bit Nyquist rate ADC for disk drive read channel applications

A CT quadrature bandpass ADC is designed for a multi-standard television receiver. When clocked at 264MHz, the ADC achieves 90dB of total DR over an 8.5MHz BW centered at 44MHz. The 4th-order 4b ADC uses a modified feedforward topology and includes 12dB of AGC. The 2.5mm2 chip consumes 375mW in a 0.18mum CMOS process