Larry Singer

A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input

This paper describes the design of a 14-b 75-Msample/s pipeline analog-to-digital converter (ADC) implemented in a 0.35-/spl mu/m double-poly triple-metal CMOS process. The ADC uses a 4-b first stage to relax capacitor-matching requirements, buffered bootstrapping to reduce signal-dependent charge injection, and a flip-around track-and-hold amplifier with wide common-mode compliance to reduce noise and power consumption. It achieves 14-b accuracy without calibration or dithering. Typical differential nonlinearity is 0.6 LSB, and integral nonlinearity is 2 LSB. The ADC also achieves 73-dB signal-to-noise ratio, and 85-dB spurious-free dynamic range over the first Nyquist band. The 7.8-mm/sup 2/ ADC operates with a 2.7- to 3.6-V supply, and dissipates 340 mW at 3 V.

A 55-mW, 10-bit, 10 Msample/s Nyquist rate CMOS ADC

A low-power 10-bit converter that can sample input frequencies above 100 MHz is presented. The converter consumes 55 mW when sampling at f/sub s/=40 MHz from a 3-V supply, which also includes a bandgap and a reference circuit (70 mW if including digital drivers with a 10-pF load). It exhibits higher than 9.5 effective number of bits for an input frequency at Nyquist (f/sub in/=f/sub s//2=20 MHz). The differential and integral nonlinearity of the converter are within /spl plusmn/0.3 and /spl plusmn/0.75 LSB, respectively, when sampling at 40 MHz, and improve to a 12-bit accuracy level for lower sampling rates. The overall performance is achieved using a pipelined architecture without a dedicated sample/hold amplifier circuit at the input. The converter is implemented in double-poly, triple-metal 0.35-/spl mu/m CMOS technology and occupies an area of 2.6 mm/sup 2/.

A 16-bit, 125 MS/s, 385 mW, 78.7 dB SNR CMOS Pipeline ADC

A 16-bit 125 MS/s pipeline analog-to-digital converter (ADC) implemented in a 0.18 ¿m CMOS process is presented in this paper. A SHA-less 4-bit front-end is used to achieve low power and minimize the size of the input sampling capacitance in order to ease drivability. The ADC includes foreground factory digital calibration to correct for capacitor mismatches and dithering that can be optionally enabled to improve small-signal linearity. This ADC achieves an SNR of 78.7 dB, an SNDR of 78.6 dB and an SFDR of 96 dB with a 30 MHz input signal, while maintaining an SNR > 76 dB and an SFDR > 85 dB up to 150 MHz input signals. Further, with dithering enabled the worst spur is <-98 dB for inputs below -4 dBFS at 100 MHz IF. The ADC consumes 385 mW from a 1.8 V supply.

A 12 b 65 MSample/s CMOS ADC with 82 dB SFDR at 120 MHz

A recent trend in cellular basestation design is to digitize multiple channels with a single ADC, often at the intermediate frequency (IF). This requires an ADC with wide dynamic range, particularly SFDR above 80 dB and SNR better than 70 dB, even when sampling input frequencies above 70 MHz. This 12b, 65MSample/s (MSPS) ADC incorporates a wide-bandwidth, low-distortion input stage coupled with a digitally-calibrated, multibit pipeline architecture optimized for low power consumption.

A 3 V 340 mW 14 b 75 MSPS CMOS ADC with 85 dB SFDR at Nyquist

A 14 b multi-bit ADC with a switched-capacitor pipeline architecture achieves 0.6 LSB DNL and 2 LSB INL without calibration. Typical SNR is 73 dB, while SFDR is >85 dB for input frequency up to Nyquist. The 7.8 mm/sup 2/ ADC in 0.35 μm double-poly triple-metal process operates with a 2.7 V to 3.6 V power supply, and consumes 340 mW at 3 V.

A 16b 125MS/s 385mW 78.7dB SNR CMOS pipeline ADC

Todays communication systems require high-performance low-cost ADCs with emphasis on low power, and the ability to IF-sample to reduce receiver complexity. Further, the often-overlooked metric of small-signal linearity, quantified by SFDR for less-than-full-scale inputs is important, especially in the presence of large interferers. This 16b pipeline ADC achieves 78.7dB SNR, 78.6dB SNDR and 96dB SFDR at 125MS/s with a 30MHz input, while dissipating 385mW from a 1.8V supply. The ADC quantizes inputs up to 150MHz with an SNR ≫76dB and an SFDR ≫85dB, has a jitter of 65fs and accepts 2Vpp-diff inputs. Further, with dithering enabled the worst spur is ≪−98dB for inputs below −4dBFS at 100MHz IF. The ADC is fabricated in a 1P5M 0.18µm CMOS process.

A 10-300-MHz IF-digitizing IC with 90-105-dB dynamic range and 15-333-kHz bandwidth

An integrated low-noise amplifier, mixer, bandpass /spl Delta//spl Sigma/ analog-to-digital converter (ADC), decimation filter, and two synthesizers implement a general-purpose back-end for a narrow-band superheterodyne receiver. The /spl Delta//spl Sigma/ ADC is merged with the mixer and combines LC, active-RC, and switched-capacitor resonators to achieve low noise and robust operation with low power consumption. A variable full-scale feature adds an automatic-gain-control capability to the ADC while saving power and minimizing noise at low signal levels.

12-b 125 MSPS CMOS D/A designed for spectral performance

A 12-b 125 MSPS, digital to analog converter fabricated on a 0.6 micron single poly double metal CMOS process is presented. The design operates on supply voltages from 2.7 to 5.5 volts and at 20 mA full. Scale output current consumes 150 mW from a 5 volt supply clocked at 100 MHz. Operating on a 3 volt supply, at 2 mA output current, and clocked at 60 MSPS, the power is less than 30 mW; new circuit architectures have been implemented which improve the spurious free dynamic range by 20 dB over previous CMOS designs and matches the results of higher power bipolar and BiCMOS designs.

A 4-channel 20-to300 Mpixel/s analog front-end with sampled thermal noise below kT/C for digital SLR cameras

We present a 4-channel analog front-end (AFE) designed specifically for multichannel sensors used in digital single-lens reflex (DSLR) cameras. Multichannel sensors have been adopted as a solution to the increasing requirements for higher throughput in imaging systems. Single-channel AFEs have been published [1–4]; however, there are drawbacks to using multiple discrete single-channel AFEs in a multichannel system. For example, column readout patterns are particularly sensitive to mismatch between AFE channels. Also, DSLR cameras support many different frame capture modes and read-out patterns, requiring clock rates from below 10MS/s to over 70MS/s, and previous AFEs have not been designed to operate over such a wide range. This paper describes several design techniques developed for the DSLR application, including adaptive power scaling, an integrated reference buffer, and a low-noise sampling technique with sampled thermal noise below kT/C.

16.7 A 12b 10GS/s interleaved pipeline ADC in 28nm CMOS technology

Software defined radios and wideband instrumentation demand the ability to digitize wide BW RF signals with moderately high dynamic range. A 12b 10GS/s ADC with an input analog bandwidth of 7.4GHz is developed for such applications in 28nm CMOS. The ADC achieves an SNR of 56dB, SNDR of 55dB and SFDR of 64dB with a 4GHz input at 10GS/s, and realizes an NSD of −157dBFS/Hz (i.e. DR = 60dB) while dissipating 2.9W.