Ivan Saraiva Silva

Pipelined Fast 2-D DCT Architecture for JPEG Image Compression

This paper presents the architecture and the VHDL design of a Two Dimensional Discrete Cosine Transform (2-D DCT) for JPEG image compression. This architecture is used as the core of a JPEG compressor and is the critical path in JPEG compression hardware. The 2-D DCT calculation is made using the 2-D DCT separability property, such that the whole architecture is divided into two I-D DCT calculations by using a transpose buffer. These parts are described in this paper, with an architectural discussion and the VHDL synthesis results as well. The 2-D DCT architecture uses 4,792 logic cells of one Altera Flex10kE FPGA and reaches an operating frequency of 12.2 MHz. One input block with 8/spl times/8 elements of 8 bits each is processed in 25.2 /spl mu/s and the pipeline latency is 160 clock cycles.

Cache coherency communication cost in a NoC-based MPSoC platform

Cache coherency and cache consistency in NoC-based heterogeneous platforms are still open problems. Current works addressing platform design avoid this issue either by proposing cacheless implementations or using snoopy protocols over buses. This paper addresses the cache coherence problem in a NoC-based MPSoC platform, focusing the communication considering both the load overhead produced by the coherency mechanism and read/write response times. Simulations of applications written in C and compiled with GCC are presented. Simulations results indicate that the load is constant with the cache size for a given line size.

When reconfigurable architecture meets network-on-chip

This paper analyzes the utilization of a network on chip (NoC) as the communication sub-system of a reconfigurable/parallel architecture. A router was designed and implemented in SystemC to analyze the NoC. With this routers the NoCX4 was created and simulated using coarse-grained reconfigurable microprocessor as processing nodes. To perform the simulation two approaches were used. The first one uses a load generator program and communication loads between 5% and 25%. The second is the calculation of 2D-DCT coefficients.

RoSA: a reconfigurable stream-based architecture

The increase of stream-based applications complexity has demanded hardware more flexible and able to reaching higher performance. Reconfigurable architectures have been showed significant progresses in exploiting the parallelism of these applications. This paper presents RoSA, a coarse-grained reconfigurable architecture that combines compilation techniques and hardware reuse to accelerate the execution of stream-based applications. The results showed that RoSA achieved performance gains of more than 74% over the code that can be executed concurrently and 55% of the total cost of the applications.

High throughput architecture for H.264/AVC forward transforms block

This paper presents a high throughput hardware for the complete H.264/AVC forward transforms block. There are three different transform inside this block and the presented architecture synchronizes these transforms, generating a constant processing rate in its outputs. This is an important characteristic of this architecture that was designed to be easily integrated to the other H.264/AVC blocks. The architecture does not use memory bits and the transforms in two dimensions are calculated directly, without the use of the separability property. The architecture was described in VHDL and was validated and prototyped using a Xilinx Virtex II Pro FPGA. The synthesis was directed to a VP30 FPGA and to a TSMC 0.35μm standard-cell technology. The throughputs of the T block architecture for these two different technologies reaches a processing rate higher than 120 million of samples per second, allowing its use in H.264/AVC codecs directed to HDTV.

X4CP32: a coarse grain general purpose reconfigurable microprocessor

The X4CP32 is a novel coarse RPU runtime-reconfigurable general purpose microprocessor. It consists of 3 programming levels, based on a hierarchical array of easily and quickly reconfigurable entities. It brings a new concept of runtime reconfiguration and programming, which is its main strength. Although it is effective in heavy arithmetic applications, it is suited for virtually any task an application can demand, presenting as a solid option for a general purpose microprocessor.

High Throughput Architecture of JPEG Compressor for Color Images Targeting FPGAs

This paper presents the design of a JPEG compressor for color images targeting high performance in a low cost FPGA device. The JPEG compressor architecture achieves high throughput with a deep and optimized pipeline and with a multiplierless datapath architecture. The architecture was synthesized to Altera FPGAs and the synthesis results and relevant performance comparisons with related works are presented. Our high throughput compressor for color images is able to compress 39.6 millions of samples per second when mapped onto an Altera FLEX 10KE low cost FPGA. Our JPEG encoder is able to compress 38 color images per second in SDTV resolution (720x480 pixels). Considering this SDTV resolution our design is worthy as a core of an M-JPEG video compressor, reaching a real time processing rate.

A FPGA based design of a multiplierless and fully pipelined JPEG compressor

This paper presents the design and implementation of a multiplierless JPEG compressor for gray scale images. The modules of this architecture were fully pipelined and targeted to FPGA device implementation. The designed architectures are detailed in this paper and they were described in VHDL, simulated and physically mapped to Altera Flex10KE FPGAs. The JPEG compressor pipeline has a minimum latency of 238 clock cycles, given the full modular pipeline depth. The minimum compressor period is 26.6ns and the compressor is able to process 37.6 millions of pixels per second. For example, the compressor can process a 640x480 pixels still image in 8.2 ms, reaching a maximum processing rate of 122.4 frames per second.

Papílio cryptography algorithm

Papilio is a Feistel cipher encryption algorithm where the coder process (function F) is based in the Viterbi algorithm. The Viterbi algorithm was proposed as a solution to decode convolutional codes. There are several parameters that define the convolution code and Viterbi algorithm; one of them is the generator polynomial. To use Viterbi algorithm in cryptography, it is necessary to make some modifications. The proposed one does not depend on the parameters of Viterbi nor on the parameters of convolution. In this work we will analyze the cryptographic indices (avalanche, diffusion and confusion) of Papilio considering all possible different polynomials and fix the other parameters.

Techniques and mechanisms for dynamic reconfiguration in an image processor

This work presents an overview of the methodology used to develop dynamic reconfiguration mechanisms for the image processor called DRIP. These techniques included in the design flow try to identify the most effective datapath and control architectures to overcome time-consuming reconfiguration delays and to provide a higher level of programmability to the reconfigurable system.