Iwao Sugiyama

Polarity of a (111)‐oriented CdTe layer grown on a (100) Si substrate

Direct epitaxial growth on silicon has advantages when fabricating monolithic integrated infrared focal‐plane arrays. We demonstrated that both (111)A and (111)B oriented CdTe layers can be grown on (100) Si substrates by molecular‐beam epitaxy. The surface morphology of the (111)A layer was rough, while that of the (111)B layer was smooth. The key determining polarity is the substrate temperature during preadsorption of Te2 flux. We found a polarity transition at 450 to 500 °C, and (111)B layers grow above that temperature.

Dislocation reduction in HgCdTe epilayers on GaAs by using CdTe/CdZnTe strained-layer superlattices in CdTe layers

Abstract The structure of CdTe/CdZnTe strained layer superlattices (SLSs) which block the threading dislocations has been studied. Since the residual strain in the heteroepitaxial CdTe offsets the SLS-induced strain, SLSs located near the interface of CdTe/GaAs should be constructed with large misfit force in place. The surface dislocation density of CdTe was found to be reduced by a factor of 2.5 by using the two SLSs, and by a factor of 4.3 for four SLSs. The etch pit density of a HgCdTe layer grown on this SLS buffer layer was reduced, a beneficial side effect of reducing the dislocations in the buffer layer. Thus, strained-layer superlattices effectively block dislocations if designed properly. The dislocation density can be further reduced by increasing the number of SLSs.

Structural properties of CdTe‐ZnTe strained‐layer superlattice grown on GaAs by hot‐wall epitaxy

CdTe‐ZnTe strained‐layer superlattices (SLSs) were grown on GaAs by hot‐wall epitaxy. The individual layer thickness of the SLS is well controlled and the thickness fluctuation is less than ±1 monolayer. High‐resolution transmission electron microscopy images show coherent SLS growth. We found that two‐thirds of the threading dislocations can be reduced by inserting the SLS in CdTe/GaAs.

Flexible Signal Processing Platform Chip for Software Defined Radio with 103 GOPS Dynamic Reconf1gurable Logic Cores

Software defined radio (SDR) is expected to be a progressive technology for wireless communications under multi-communication systems. SDR requires high performance, low power consumption, and short latency hardware. We have developed a single-chip baseband processing LSI for SDR based on a hybrid architecture of coarse-grain reconfigurable logic cores and flexible accelerator modules to achieve the required features. The maximum performance is 103 GOPS. Moreover, we implemented IEEE 802.11a and IEEE 802.11b, and show the effectiveness in latency.

Dislocation interactions in CdTe/GaAs grown by hot wall epitaxy with CdTe/CdZnTe superlattices

Abstract CdTe epilayers grown on GaAs (001) containing two CdTe/CdZnTe superlattices (SLSs) have been examined by TEM. The overall dislocation-reduction effect from plan-view measurements is found to be 2.5 times, with the bending of threading dislocations occuring largely at the top and bottom layers in each of the SLSs. However, it is found that a large number of threading dislocations in the epilayer exist in the form of dipole pairs. In particular, long straight dislocations (LSDs) originating from the interface region are almost always close dipole pairs with typical spacings of less than 10 nm between the components. A model is presented to explain the formation of such LSD dipoles at the early stages of growth. It is proposed that dislocations with opposite Burgers vectors gliding on parallel {111} planes interact to form close dipole pairs elongated in 〈112〉 directions. It is shown that the pairing of dislocations in this manner reduces the effectiveness of SLS layers in dislocation filtering. In addition, the dislocations in the dipole pairs are frequently found to be dissociated into two partial dislocations. These effects complicate the dynamics of dislocations in CdTe/GaAs and may place a serious constraint on the ability of SLSs to remove threading dislocations from these epilayers.

Study on Deep Level Traps in p-HgCdTe With Dltfs

The authors studied the characteristics of deep-level traps in p-type HgCdTe diodes using the Deep Level Transient Fourier Spectroscopy (DLTFS) method. For both holes and electrons, two types of traps were observed. The DLTFS signal intensity of one type of trap increased with the carrier density in the HgCdTe, while the other did not exhibit a monotonic increase. While measuring the stability of these traps during cooling cycles, the DLTFS signal intensity of the first group was almost constant while that of the latter fluctuated with every cooling cycle. Stable traps originated from Hg vacancies, unstable traps are attributed to vacancy-impurity complex defects.

A Highly Sensitive And Compact SO2 Gas Sensor Using A Pbsnte Laser

We have developed a highly sensitive, compact SO2 gas sensor that uses a PbSnTe laser. To increase its sensitivity, we used wedge-shaped windows that decrease etalon fringes and a SO2 absorption line that is little influenced by water vapor and that has a strong coefficient. The etalon-fringe intensity of the optical system was reduced to 1 x 10-4 and the SO2 absorption line selected is 1380.9 cm-1. To make the sensor compact, we developed single-mode lasers to eliminate the need for a monochromator, used a 30-cm multipath cell with an optical path of 10 m and a liquid-nitrogen-cooled, small metal dewar to cool the laser. The sensor performs stably at 30 ppb over a range of 10°C to 35°C, has a sensitivity of 7 ppb RMS at a fixed temperature, and is 32 cm x 50 cm x 20 cm.