Katsuhiro Yoda

Flexible Signal Processing Platform Chip for Software Defined Radio with 103 GOPS Dynamic Reconf1gurable Logic Cores

Software defined radio (SDR) is expected to be a progressive technology for wireless communications under multi-communication systems. SDR requires high performance, low power consumption, and short latency hardware. We have developed a single-chip baseband processing LSI for SDR based on a hybrid architecture of coarse-grain reconfigurable logic cores and flexible accelerator modules to achieve the required features. The maximum performance is 103 GOPS. Moreover, we implemented IEEE 802.11a and IEEE 802.11b, and show the effectiveness in latency.

Energy efficient Echo-Hiding extraction method based on fine grain intermittent power control

We propose a low power extraction method of Echo-Hiding audio steganography. Our intermittent power control strategy enables to reduce the active time of devices including processor, ADC, and sensors. Our strategy consists of two features; majority-rule extraction method reduces the active time during extraction, and intermittent watermark detection enables the devices to be almost powered off in the environment without watermarked audio. In the experiments, our method reduced the active time of the processor and ADC to 60-70%. Also, in the environment without watermarked audio, our method was able to reduce 99% of the active time.

Peak power reduction of a sensor network processor fabricated with Deeply Depleted Channel transistors in 65nm technology

We fabricated a low power sensor network processor with Deeply Depleted Channel (DDC) transistors of 65 nm technology, which has distinguishing device structure and enables variation of threshold voltage (Vth) of transistors to decrease. At the optimal voltage condition to achieve the same maximum operating frequency, measurement result shows that the DDC process achieves a 47.0 % of peak power reduction for the micro controller unit (MCU) compared to the conventional low power (LP) process. Measurement result also shows the DDC process improves 56.5 % and 15.0 % of operating frequency, 200 mV and 50 mV of supply voltage margin, or 23.8 % and 19.0 % of power reduction for the MCU and 320 KB SRAM, respectively, even if the Vth of the LP process is adjusted to that of the DDC process. The paper has also discussed the optimal voltage control method, which is suitable for the various applications of sensor network processors.