Izhal Abdul Halin

A QVGA-size CMOS time-of-flight range image sensor with background light charge draining structure

3-D imaging systems can be used in a variety of applications such as in automobile, medicine, robot vision systems, security and so on. Recently many kinds of range finding methods have been proposed for 3-D imaging systems. This paper presents a new type of CMOS range image sensor based on the Time-of-Flight (TOF)principle with a spatial resolution of 336 × 252 (QVGA) and pixels of 15 × 15 μm2 size. A pixel structure of the sensor consists of single layer polysilicon gates on thick field oxide and has a function of background light induced charge reduction. The chip was fabricated in a 0.35 μm standard CMOS process with two poly and three metal layers. The presented sensor achieves a minimum range resolution of 2.8cm at framerate of 30fps and the resolution is improved to 4.2mm for 10 frames averaging, which corresponds to 3fps.

A 10 ps Time-Resolution CMOS Image Sensor With Two-Tap True-CDS Lock-In Pixels for Fluorescence Lifetime Imaging

A CMOS lock-in pixel image sensor with embedded storage diodes and lateral electric field modulation (LEFM) of photo-generated charge is developed for fluorescence lifetime imaging. The time-resolved CMOS image sensor (CIS) with twotap lock-in pixels achieves a very high time resolution of 10 ps when images are averaged over 30 frames, a very short intrinsic response time of 180 ps at 374 nm, and a low temporal random noise of 1.75e-rms with true correlated double sampling (CDS) operation. In addition, by using the LEFM and optimized process, a very high extinction ratio of approximately 94% at 472 nm laser diode is achieved. The usefulness of the proposed CIS is demonstrated for fluorescence lifetime imaging with the simulation and measurement results.

Non-Linearity in Wide Dynamic Range CMOS Image Sensors Utilizing a Partial Charge Transfer Technique

The partial charge transfer technique can expand the dynamic range of a CMOS image sensor by synthesizing two types of signal, namely the long and short accumulation time signals. However the short accumulation time signal obtained from partial transfer operation suffers of non-linearity with respect to the incident light. In this paper, an analysis of the non-linearity in partial charge transfer technique has been carried, and the relationship between dynamic range and the non-linearity is studied. The results show that the non-linearity is caused by two factors, namely the current diffusion, which has an exponential relation with the potential barrier, and the initial condition of photodiodes in which it shows that the error in the high illumination region increases as the ratio of the long to the short accumulation time raises. Moreover, the increment of the saturation level of photodiodes also increases the error in the high illumination region.

A review on Solid State time of flight TOF range image sensors

This paper reviews three different types of Solid State time of flight TOF range image sensors. All of the sensors studied measure range by detecting the TOF of light using three different methods which are pulse modulation, sine wave modulation and time to digital converter TOF range image sensors. From the review it is found that the Power Dissipation of the SPAD i.e. single photon avalanche diode TOF image sensor is lowest which is 750uw. Range Resolution of the GOFO i.e. gate on field oxide structure TOF range image sensor is smaller which 2.35cm at 30fps and finally the Spatial Resolution of the GOFO TOF image sensor is largest which is 336 × 252 pixels.

A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance

A review on CMOS delay lines with a focus on the most frequently used techniques for high-resolution delay step is presented. The primary types, specifications, delay circuits, and operating principles are presented. The delay circuits reported in this paper are used for delaying digital inputs and clock signals. The most common analog and digitally-controlled delay elements topologies are presented, focusing on the main delay-tuning strategies. IC variables, namely, process, supply voltage, temperature, and noise sources that affect delay resolution through timing jitter are discussed. The design specifications of these delay elements are also discussed and compared for the common delay line circuits. As a result, the main findings of this paper are highlighting and discussing the followings: the most efficient high-resolution delay line techniques, the trade-off challenge found between CMOS delay lines designed using either analog or digitally-controlled delay elements, the trade-off challenge between delay resolution and delay range and the proposed solutions for this challenge, and how CMOS technology scaling can affect the performance of CMOS delay lines. Moreover, the current trends and efforts used in order to generate output delayed signal with low jitter in the sub-picosecond range are presented.

11.2 A 10.8ps-time-resolution 256×512 image sensor with 2-Tap true-CDS lock-in pixels for fluorescence lifetime imaging

Fluorescence lifetime imaging microscopy (FLIM), which is a nondestructive and minimally invasive manner and can therefore be applied to living cells and tissues, is a great analysis tool in fundamental physics as well as in the life sciences. Charge-coupled devices (CCDs) [1] and single-photon avalanche diodes (SPADs) [2,3] are used for time-resolved lifetime measurement. In particular, SPAD-based time-resolved imagers have a high single-photon sensitivity and good noise robustness. However, they consist of a SPAD array with pixel circuitry, time-to-digital converters (TDCs), digital integrators to amplify signals, and readout circuitry. To implement the high photon-counting rate, a large number of TDCs and digital integrators are required. The spatial resolution of the SPAD-based time-resolved imagers is limited on this account. A recently reported time-resolved CMOS imager [4] using a draining-only modulation (DOM) technique has an attractive feature that a very simple pixel structure and 2-stage charge transfer without transfer gate (TG) can be simultaneously attained. However, it has a small aperture area, a comparatively low transfer speed, and multiple outputs are a challenge.

The data and read/write controller for March-based SRAM diagnostic algorithm MBIST

This paper presents the implementation of March-based algorithm as proposed in [1] into an Memory Built-in Self-Test (MBIST) data and read/write controller. The design uses the7 approach of Finite S täte M achine (FSM)-based a rchitecture which is more plausible since the design was part of the engine that will be exclusively developed for the testing of this algorithm alone. This controller will represent a portion of MBIST engine that can be incorporated together with other portions to build a complete MBIST engine.

Design of front end of a RF receiver

Radio frequency (RF) circuit is having a rapid growth in wireless telecommunication. The increasing demand for higher quality and popularity of wireless services have urged the development of low cost multi-functional and reconfigurable RF front end modules fabricated from advanced device technologies. The RF front end is generally defined as everything between antenna and the intermediate frequency (IF) stage. For a receiver, this “between” area in eludes filter, low noise amplifier, mixer and local oscillator. The circuit w as designed based on CMOS 0.18um technology to input a 2. 5 GHz RF signal and local oscillation of 2.25 GHz. This results in an output IF frequency of 250 MHz. The RF front end circuit had been simulated using Advanced Design System to ob tain the proper output frequency and determining the system performance.

The demand model of electric field strength on microelectrode designed for AC electrokinetic applications

This paper presents an investigation of electric field strength using the Multi-Physics Finite Element Solution Environment for Partial Differential Equations, FlexPDE. It is to give an idea on the flow of particles in lab on a chip (LoC) and bioMEMS devices when they passed through the active microelectrode array using one of the AC electrokinetic techniques that is dielectrophoresis. The field strength regions can give an overview of particle motion either to high electric field strength or to low electric field strength in relation to the dielectrophoretic force. The results from this investigation will be used to justify the direction of particles flow in the LoC device during experimental work.

Low Power Transmitter for Wireless Capsule Endoscope

This paper presents the transmitter circuit designed for the application of wireless capsule endoscope to overcome the limitation of conventional endoscope. The design is performed using CMOS 0.13 μm technology. The transmitter is designed to operate at centre frequency of 433.92 MHz, which is one of the ISM band. Active mixer and ring oscillator made up the transmitter and it consumes 1.57 mA of current using a supply voltage of 1.2 V, brings the dc power consumption of the transmitter to be 1.88 mW. Data rate of 3.5 Mbps ensure it can transmit high quality medical imaging.