Roslina Mohd Sidek

Design of a micro-UART for SoC application

Abstract This paper presents the design of a universal asynchronous receiver and transmitter (UART), which is fully functional and synthesizeable. Due to its modularity, configurability and extremely compact size, the proposed UART is named as micro-UART and it is ideal for system-on-a-chip (SoC) application. The core is usable as an intellectual property. Verilog hardware description language (HDL) in the Alteras MAX-PLUS II environment has been used for its design, compilation and simulation. The UART has been implemented using Alteras FPGA technology.

Efficiency improvement in microwave power amplifiers by using Complex Gain Predistortion technique

Power Amplifiers (PAs) are important parts of the transmitters. They amplify the signals that are going to be transmitted. With increasing the input power of the PA, it creates the nonlinearity at the output. The nonlinearity causes out of band distortion and in band distortion. To overcome these effects the power amplifier should be backed off but it will reduce the efficiency of the PA. To increase the efficiency, the Complex Gain Memory Predistortion (CGP) is added to the system. Experimental results with the Mini Circuit power amplifier show an improvement of 7% in Power Added Efficiency (PAE) when the CGP method is applied.

Challenges and directions for testing IC

In todays semiconductor world, integration technology is improving and refining dramatically. With the continuous increase of integration densities and complexities, the problem of integrated circuit (IC) testing has become much more acute. IC testing is now no more a back-end issue, rather it has become a front-end burning issue, which needs an economic solution with reliable performance. Otherwise all the benefits of semiconductor technology would be meaningless. A roadmap of semiconductor technology in the context of IC testing is shown in this paper. Researchers and manufacturers can get to know current challenges and directions of IC testing through this discussion.

A low complexity selected mapping scheme for peak to average power ratio reduction with digital predistortion in OFDM systems

One of the effective methods used for reducing peak-to-average power ratio (PAPR) in orthogonal frequency division multiplexing (OFDM) systems is selected mapping (SLM). In this paper, a new SLM scheme called DSI-SLM, which is a combination of dummy sequence insertion (DSI) and conventional selected mapping (C-SLM) is proposed. Previous techniques have had some drawbacks. In DSI, increasing the number of dummy sequences to have better PAPR degrades transmission efficiency, and in C-SLM, the complexity rises dramatically when the number of sub-blocks increases. The proposed DSI-SLM scheme significantly reduces the complexity because of the reduction in the number of sub-blocks compared with the C-SLM technique while its PAPR performance is even better. To enhance the efficiency of the OFDM system and suppress the out-of-band distortion from the power amplifier nonlinearity, a digital predistortion technique is applied to the DSI-SLM scheme. Simulations are carried out with the actual power amplifier model and the OFDM signal based on the worldwide interoperability for microwave access standard and quadrature phase-shift keying modulation. The simulation results show improvement in PAPR reduction and complexity, whereas the BER performance is slightly worse.

Investigations on a Novel Inductive Concept Frequency Technique for the Grading of Oil Palm Fresh Fruit Bunches

From the Malaysian harvesters perspective, the determination of the ripeness of the oil palm (FFB) is a critical factor to maximize palm oil production. A preliminary study of a novel oil palm fruit sensor to detect the maturity of oil palm fruit bunches is presented. To optimize the functionality of the sensor, the frequency characteristics of air coils of various diameters are investigated to determine their inductance and resonant characteristics. Sixteen samples from two categories, namely ripe oil palm fruitlets and unripe oil palm fruitlets, are tested from 100 Hz up to 100 MHz frequency. The results showed the inductance and resonant characteristics of the air coil sensors display significant changes among the samples of each category. The investigations on the frequency characteristics of the sensor air coils are studied to observe the effect of variations in the coil diameter. The effect of coil diameter yields a significant 0.02643 MHz difference between unripe samples to air and 0.01084 MHz for ripe samples to air. The designed sensor exhibits significant potential in determining the maturity of oil palm fruits.

A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance

A review on CMOS delay lines with a focus on the most frequently used techniques for high-resolution delay step is presented. The primary types, specifications, delay circuits, and operating principles are presented. The delay circuits reported in this paper are used for delaying digital inputs and clock signals. The most common analog and digitally-controlled delay elements topologies are presented, focusing on the main delay-tuning strategies. IC variables, namely, process, supply voltage, temperature, and noise sources that affect delay resolution through timing jitter are discussed. The design specifications of these delay elements are also discussed and compared for the common delay line circuits. As a result, the main findings of this paper are highlighting and discussing the followings: the most efficient high-resolution delay line techniques, the trade-off challenge found between CMOS delay lines designed using either analog or digitally-controlled delay elements, the trade-off challenge between delay resolution and delay range and the proposed solutions for this challenge, and how CMOS technology scaling can affect the performance of CMOS delay lines. Moreover, the current trends and efforts used in order to generate output delayed signal with low jitter in the sub-picosecond range are presented.

Design of ultra-low voltage 0.5V CMOS current bleeding mixer

This paper presents an ultra-low voltage and low power current bleeding CMOS double balanced mixer targeted for ZigBee application in 2.4GHz frequency band. It introduces and discusses a modified CMOS based current bleeding mixer topology adopting a combination of NMOS current bleeding transistor, with a PMOS Local Oscillator (LO) switching stage and integrated inductors to achieve ultra-low voltage headroom operation at 0.5V. This mixer is simulated and verified in 0.13µm standard CMOS technology. The result shows a conversion gain (CG) of 11.84dB, 1dB compression point (P1dB) at -14.36dBm, third-order intercept point (IIP3) of -5dBm and a noise figure (NF) of 15dB and with a power consumption of 930µW.

A new DSI-SLM method for PAPR reduction in OFDM systems

High PAPR is the main drawback of OFDM systems. DSI method and SLM method are two of the most promising techniques to reduce PAPR.

RC4A stream cipher for WLAN security: A hardware approach

Wireless networks are on the cutting edge of modern technology and rapidly gaining popularity in todaypsilas world due to their excellent usability. For secure wireless data transmission, Wired Equivalent Privacy (WEP), IEEE 802.11 standard defined security protocol, is employed. WEP has a potential limitation that stems from its adaptation of RC4 stream cipher algorithm. As a result, there is a pressing need for new WLAN security measure. Therefore, this paper presents hardware implementation of RC4A stream cipher and proposes to replace RC4 in WLAN security scheme, due to weakness of RC4.The design of the cipher was implemented by Verilog HDL. For hardware implementation of the design, an Altera Field Programmable Gate Array (FPGA) device, EP20K200EFC484-2X from APEX family, APEX 20KE, was used.

12N test procedure for NPSF testing and diagnosis for SRAMs

Testing and diagnosis techniques play a key role in the advance of semiconductor memory technologies. The challenge of failure detection has attracted investigation on efficient testing and diagnosis algorithm for better fault coverage and diagnostic resolution. March algorithms are widely used in SRAM testing to detect and diagnose SRAM fault model since they are relatively simple and yet providing high fault coverage and diagnostic resolution. In this case to achieve high fault coverage the structure of the consecutive memory backgrounds are very important. This paper aims to prove the efficiency of March 12N algorithm in term of detection and identification capability and locate the NPSF model fault. The details of test and diagnosis procedures for NPSF are demonstrated in this paper. The fault detection and diagnostic of the SRAM memories in this paper is verified and proven. The required march elements, detection requirement, detection conditions and fault syndromes are also enlightened. Furthermore, these particulars are required to determine a good algorithm other applications.