Izumi Nitta

Non-Gaussian statistical timing models of die-to-die and within-die parameter variations for full chip analysis

Statistical timing analysis (SSTA) is a method that calculates circuit delay statistically with process parameter variations, die-to-die (D2D) and within-die (WID) variations. In this paper, we model that WID parameter variations are independent for each cell and line in a chip and D2D variations are governed by one variation on a chip. We propose a new method of computing a full chip delay distribution considering both D2D and WID parameter variations. Experimental results show that the proposed method is more accurate than previous methods on actual chip designs.

Speed-path analysis for multi-path failed latches with random variation

In processor and high-end chip designs, path delay difference between pre-silicon and post-silicon have become an important issue. Identifying the factors for the difference with speed limiting paths is required to achieve target performance. A statistical diagnosis framework, called speed-path analysis, identifies them. Speed-path analysis uses fail data from at-speed delay test with silicon samples. Since at-speed delay test activates multiple paths simultaneously, it makes many failed latches with multiple sensitized paths. We will refer to these failed latches as multi-path failed latches. Previous works have not discussed how to handle multi-path failed latches because they are discussions under the assumption that path delay differences are obtained correctly. Generating additional test patterns to activate a single path for each latch is a very time-consuming task. Without using multi-path failed latches from at-speed delay test, the fatal factors for path delay differences with speed limiting paths can be missed because the number of non multi-path failed latches is small. This paper proposes methods for handling multi-path failed latches. By experiments based on a test processor design, we can deal with 12% of the timing-critical latches adopted as failed latches while 1% using only non multi-path failed latches.

A fuzzy pattern matching method based on graph kernel for lithography hotspot detection

In advanced technology nodes, lithography hotspot detection has become one of the most significant issues in design for manufacturability. Recently, machine learning based lithography hotspot detection has been widely investigated, but it has trade-off between detection accuracy and false alarm. To apply machine learning based technique to the physical verification phase, designers require minimizing undetected hotspots to avoid yield degradation. They also need a ranking of similar known patterns with a detected hotspot to prioritize layout pattern to be corrected. To achieve high detection accuracy and to prioritize detected hotspots, we propose a novel lithography hotspot detection method using Delaunay triangulation and graph kernel based machine learning. Delaunay triangulation extracts features of hotspot patterns where polygons locate irregularly and closely one another, and graph kernel expresses inner structure of graphs. Additionally, our method provides similarity between two patterns and creates a list of similar training patterns with a detected hotspot. Experiments results on ICCAD 2012 benchmarks show that our method achieves high accuracy with allowable range of false alarm. We also show the ranking of the similar known patterns with a detected hotspot.

A volume diagnosis method for identifying systematic faults in lower-yield wafer occurring during mass production

This work focuses on volume diagnosis for identifying systematic faults in lower-yield wafers, whose yields are lower than baseline level due to systematic faults during mass production. We develop a model-based volume diagnosis method. To diagnose accurately using the fail data with one lower-yield wafer, we apply modeling techniques for handling pseudo-faults and random faults in the fail data. Experimental results show our methods efficiency; we succeeded in identifying the failure layer for 20/22 data sets with actual lower-yield wafers.

“Condition-based” dummy fill insertion method based on ECP and CMP predictive models

Chemical Mechanical Polishing (CMP)-aware design has become important for reliability and yield. Recent work on predictive models for wafer surface planarity of Cu CMP has proven that the variation of wafer surface planarity is impacted by the metal perimeter in addition to the pattern density. Dummy fill insertion has been widely adopted to improve the CMP planarity in industrial design flows. However, conventional dummy fill insertion has been derived mainly to optimize the pattern density uniformity, which may worsen the CMP planarity because of missing impacts due to metal perimeter. In this paper, we propose; 1) a design of experiment (DOE) based method of evaluating the quality of fill insertion by using a CMP simulator which considers the impacts due to both pattern density and metal perimeter, and 2) a condition-based dummy fill insertion using the results of the proposed DOE method. Compared to the conventional pattern density driven rule-based fill insertion, the proposed method reduces the post-CMP Cu surface height variation by 24.3%. The metric of the metal perimeter may be applied to the model-based fill insertion methods, which will improve the planarity in the practical fill insertion flow.