Yuzi Kanazawa

Generation of yield-embedded Pareto-front for simultaneous optimization of yield and performances

As the variations of shrunk processes increasing at rapid rate, the performances of analog/mixed-signal chips remarkably fluctuate. It is necessary to take the yield as a design objective in design optimization. This paper presents a novel method to generate yield-embedded Pareto-front to simultaneously optimize both the yield and performances. Unlike the traditional approaches which generate the yield-aware Pareto-front to optimize performances for the fixed yield, this work embeds the yield as an objective of the optimization and evolutionarily optimizes both yield and performances by the so-called yield-embedded NSGA. The experiments demonstrate the gradual evolutions and global searching for the better performances and higher yields under PVT variations. The generation accelerated by parallel computations gains 4.8x speedup with 80% efficiency.

Speed-path analysis for multi-path failed latches with random variation

In processor and high-end chip designs, path delay difference between pre-silicon and post-silicon have become an important issue. Identifying the factors for the difference with speed limiting paths is required to achieve target performance. A statistical diagnosis framework, called speed-path analysis, identifies them. Speed-path analysis uses fail data from at-speed delay test with silicon samples. Since at-speed delay test activates multiple paths simultaneously, it makes many failed latches with multiple sensitized paths. We will refer to these failed latches as multi-path failed latches. Previous works have not discussed how to handle multi-path failed latches because they are discussions under the assumption that path delay differences are obtained correctly. Generating additional test patterns to activate a single path for each latch is a very time-consuming task. Without using multi-path failed latches from at-speed delay test, the fatal factors for path delay differences with speed limiting paths can be missed because the number of non multi-path failed latches is small. This paper proposes methods for handling multi-path failed latches. By experiments based on a test processor design, we can deal with 12% of the timing-critical latches adopted as failed latches while 1% using only non multi-path failed latches.

A fuzzy pattern matching method based on graph kernel for lithography hotspot detection

In advanced technology nodes, lithography hotspot detection has become one of the most significant issues in design for manufacturability. Recently, machine learning based lithography hotspot detection has been widely investigated, but it has trade-off between detection accuracy and false alarm. To apply machine learning based technique to the physical verification phase, designers require minimizing undetected hotspots to avoid yield degradation. They also need a ranking of similar known patterns with a detected hotspot to prioritize layout pattern to be corrected. To achieve high detection accuracy and to prioritize detected hotspots, we propose a novel lithography hotspot detection method using Delaunay triangulation and graph kernel based machine learning. Delaunay triangulation extracts features of hotspot patterns where polygons locate irregularly and closely one another, and graph kernel expresses inner structure of graphs. Additionally, our method provides similarity between two patterns and creates a list of similar training patterns with a detected hotspot. Experiments results on ICCAD 2012 benchmarks show that our method achieves high accuracy with allowable range of false alarm. We also show the ranking of the similar known patterns with a detected hotspot.

A volume diagnosis method for identifying systematic faults in lower-yield wafer occurring during mass production

This work focuses on volume diagnosis for identifying systematic faults in lower-yield wafers, whose yields are lower than baseline level due to systematic faults during mass production. We develop a model-based volume diagnosis method. To diagnose accurately using the fail data with one lower-yield wafer, we apply modeling techniques for handling pseudo-faults and random faults in the fail data. Experimental results show our methods efficiency; we succeeded in identifying the failure layer for 20/22 data sets with actual lower-yield wafers.