İzzet Cem Göknar

A canonical representation for piecewise-affine maps and its applications to circuit analysis

A canonical representation for a rather general class of piecewise-affine maps has been developed. This canonical representation extends the canonical representation proposed by L.O. Chua and S.M. Hang (Proc. IEEE, vol.65, no.6, p.915-29, 1977) into PWA (piecewise-affine) partitions, which arise frequently in driving-point, transfer characteristics, and state equations. Thus, a universal canonical representation that is capable of characterizing circuit equations, state equations, and driving-point and transfer characteristics of piecewise-affine circuits in a compact global analytic form has been obtained. The canonical forms developed seem to be promising tools for computational purposes as well as for analytical studies of PWA circuits. >

Obtaining the inverse of the generalized Vandermonde matrix of the most general type

A step-by-step simple procedure for finding the inverse of the generalized Vandermonde matrix of the most general type is presented.

Memstor, memstance simulations via a versatile 4-port built with new adder and subtractor circuits

In this paper, novel voltage-mode (VM) n-channel metal-oxide semiconductor (NMOS) transistor-based analogue adder and subtractor circuits, which, respectively, perform V1+V2 and V1−V2 operations, are presented. The most important feature of the proposed circuits is their extremely simple structures containing only six NMOS transistors. Further, the presented adder and subtractor circuits have high input and low output impedances, resulting in easy cascadability. The post-layout simulations of the proposed circuits have been executed using TSMC 0.25 µm process parameters with ±1.25 V. The area of the suggested circuits is approximately 30 × 13 µm2. Moreover, the topology of a generalised mutator, a versatile 4-port built with an adder and a subtractor, which acts as an ordinary mutator when properly reduced to a 2-port, is offered. A table for simulating lossless inductance, memristor, meminductor, memcapacitor and other elements under suitable termination of the 4-port is given, and three of these elements’ simulations with SPICE are also presented.

New Memristor Applications: AM, ASK, FSK, and BPSK Modulators

Implementations of amplitude (AM), amplitude-shift keying (ASK), frequency-shift keying (FSK), and binary phase-shift keying (BPSK) modulators with memristors are presented as new applications. The proposed modulators operate in current mode. They contain a preprocessing circuit that converts unipolar bit sequences into an appropriate form for modulation with at most two memristors. Using the memristor model developed by Biolek et al., PSPICE simulations of the proposed modulators that verify the mathematical derivations are presented.

A CMOS Classifier Circuit Using Neural Networks With Novel Architecture

In this letter, complementary metal-oxide-semiconductor (CMOS) implementation of a neural network (NN) classifier with several output levels and a different architecture is given. The proposed circuit operates in current mode and can classify several types of data. The classifier circuit is designed using a current-voltage converter, an inverter followed by a NOR gate and a voltage-current output stage. Using a 0.35-m TSMC technology parameters, SPICE simulation results for a classifier with two inputs are included to verify the expected results.

MOMCO: method of moment components for passive model order reduction of RLCG interconnects

We introduce a new concept called moment components and a new method based on it to obtain passive reduced-order models of interconnect networks. In this method, the impedance matrix moments of the interconnect network are partitioned into their inductive, capacitive and mixed inductive/capacitive moment components. The method of moment components is described in a formal manner using analysis and synthesis equalities. Two significant contributions of the method of moment components are: 1) new decomposition of moments into parts which reflect passivity in all moments of passive networks; and 2) the analysis equalities impart a regular pattern in terms of the moment components, thus simplifying the moment generation for our method. None of these features is observable in conventional complete moment terms. Two new methods for obtaining passive reduced-order models based on the method of moment components are introduced. The passive reduced-order models are obtained by matching their impedance moment components to those of the original interconnect network through the synthesis equalities. Due to nonnegative definiteness of the moment components, the match in the moment components preserves the passivity of the original interconnect in the reduced-order model. The method of moment components does not have the instability problem of general moment matching techniques. The reduced-order model is specifically targeted for fast timing simulators so that interconnect effects can be simulated efficiently.

An intelligent balance

This paper discusses the intelligent balance, which has been established between real and virtual experiments and it also gives skills that have not covered in conventional electronics and communication engineering. Engineering is the art of applying scientific and mathematical principles, experience, judgment and common sense to make things that benefit people. The explosive growth of computer capabilities and easy access to nanominiature devices has revolutionized communication and the analysis of complex systems. The EC engineer either individually or as a member of a team, can play an important role in this technical diverse mosaic and this community prepares to adapt frequency shifts in technical priorities. EC engineers should be given computers hand-on-practice and training and also should understand the physics of the problem and fundamental theorem.

Cellular neural network with trapezoidal activation function

This paper presents a cellular neural network (CNN) scheme employing a new non-linear activation function, called trapezoidal activation function (TAF). The new CNN structure can classify linearly non-separable data points and realize Boolean operations (including eXclusive OR) by using only a single-layer CNN. In order to simplify the stability analysis, a feedback matrix W is defined as a function of the feedback template A and 2D equations are converted to 1D equations. The stability conditions of CNN with TAF are investigated and a sufficient condition for the existence of a unique equilibrium and global asymptotic stability is derived. By processing several examples of synthetic images, the analytically derived stability condition is also confirmed. Copyright

Interconnect simulation in a fast timing simulator ILLIADS-I

This paper presents a new technique to simulate RLC/RC interconnects and driving nonlinear circuits with high computational efficiency. We introduce ILLIADS-I, a fast transistor-level timing simulator for MOS circuits driving RLC/RC interconnects. The RLC/RC interconnect networks are reduced to an appropriate model and then simulated in the timing simulator as a modified generic circuit primitive. The accuracy and speed have been demonstrated for a number of circuits for various loads and input waveforms. Experimental results show ILLIADS-I is both accurate and fast. The speed advantage Is shown to increase with the circuit size for multilevel interconnect networks with nonlinear driver and load circuits.

On the state description of nonlinear networks

It is shown through an example that solutions of differential equations obtained from a network do not satisfy network constraints. A general discussion is provided which demonstrates that state equations in terms of charges and fluxes offer a better representation of the network.