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Memstor, memstance simulations via a versatile 4-port built with new adder and subtractor circuits

In this paper, novel voltage-mode (VM) n-channel metal-oxide semiconductor (NMOS) transistor-based analogue adder and subtractor circuits, which, respectively, perform V1+V2 and V1−V2 operations, are presented. The most important feature of the proposed circuits is their extremely simple structures containing only six NMOS transistors. Further, the presented adder and subtractor circuits have high input and low output impedances, resulting in easy cascadability. The post-layout simulations of the proposed circuits have been executed using TSMC 0.25 µm process parameters with ±1.25 V. The area of the suggested circuits is approximately 30 × 13 µm2. Moreover, the topology of a generalised mutator, a versatile 4-port built with an adder and a subtractor, which acts as an ordinary mutator when properly reduced to a 2-port, is offered. A table for simulating lossless inductance, memristor, meminductor, memcapacitor and other elements under suitable termination of the 4-port is given, and three of these elements’ simulations with SPICE are also presented.

A flexible current-mode classifier circuit and its applications

In this paper a new CMOS classifier circuit is presented, simulated, and compared with other recently introduced circuits. The proposed CMOS circuit operates in current-mode and can classify several types of data. The architecture is designed using two threshold circuits and a subtraction circuit. Among many possible applications of the classifier circuit, template-based pattern classification, namely template matching and character recognition with corruption, and in another direction its use as a quantizer are given. Using 0.35- µm AMS technology parameters, SPICE simulations as well as hard realization results for the classifier and application circuits are included; detailed Monte Carlo analyses to assess parameter mismatch effects are also performed. Copyright

High performance CMOS realization of the third generation current conveyor (CCIII)

In this paper a new CMOS high performance dual-output realization of the third generation current conveyor (CCIII) is presented. The proposed CCIII provides good linearity, high output impedance at port Z and excellent input/output current gain. PSPICE simulation results using the MIETEC 1.2 /spl mu/m CMOS process model are included to verify the expected values.

HIGH-SLEW RATE LOW-QUIESCENT CURRENT RAIL-TO-RAIL CMOS BUFFER AMPLIFIER FOR FLAT PANEL DISPLAYS

This work presents a high-slew rate rail-to-rail buffer amplifier, which can be used for flat panel displays. The proposed buffer amplifier is composed of two transconductance amplifiers, two current comparators and a push-pull output stage. Phase compensation technique is also used to improve the phase margin value of the proposed buffer amplifier for different load capacitances. Post-layout simulations of the proposed buffer amplifier are performed using 0.35 μm AMS CMOS process parameters and 3.3 V power supply. The circuit is tested under a 600 pF capacitive load. An average settling time of 0.85 μs under a full voltage swing is obtained, while only 3 μA quiescent current is drawn from the power supply. Monte Carlo analysis is also added to show the process variation effects on the circuit.

Linearly weighted classifier circuit

In this paper a CMOS realization of a linearly weighted classifier circuit which is called classifier block is proposed. The proposed classifier block is composed of Linearly Weighted Circuits (LWC) and CMOS Core Circuits (CC). The proposed circuit can classify linearly non-separable data. The weights of the classifier circuit are achieved with LWC blocks. Using 0.35 μm AMS technology parameters, SPICE simulation results for a LWC and classifier block are included to verify the expected results.

A compact rail-to-rail CMOS buffer amplifier with very low quiescent current

In this work, a very compact, rail-to-rail, high-speed buffer amplifier for liquid crystal display (LCD) applications is proposed. Compared to other buffer amplifiers, the proposed circuit has a very simple architecture, occupies a small number of transistors and also has a large driving capacity with very low quiescent current. It is composed of two complementary differential input stages to provide rail-to-rail driving capacity. The push–pull transistors are directly connected to the differential input stage, and the output is taken from an inverter. The proposed buffer circuit is laid out using Mentor Graphics IC Station layout editor using AMS 0.35 μm process parameters. It is shown by post-layout simulations that the proposed buffer can drive a 1 nF capacitive load within a small settling time under a full voltage swing, while drawing only 1.6 μA quiescent current from a 3.3 V power supply.

Pulse Width Modulation using a recently developed CMOS core circuit

In this paper a new approach for a Pulse Width Modulation (PWM) circuit operating in current-mode using a CMOS classifier core circuit, and its application to level crossing are presented. The proposed architecture is much simpler than existing PWM methods and the generated PWM signal can be controlled electronically through the control currents of a core circuit. Measurements performed with DU-TCC 1209*, an IC designed and manufactured using 0.35 μm AMS technology parameters, show a perfect match with theoretical results.

A low-power multilevel-output classifier circuit

A low power CMOS implementation of a multi- input data classifier with several output levels is presented. The proposed circuit operates in current-mode and can classify several types of analog vector data. An architecture is developed comprising a threshold circuit which operates in sub-threshold region. Using 0.35 mum TSMC technology parameters, SPICE simulation results for a classifier with two inputs are included to verify the anticipated results.

MOS only oscillator using adder and subtractor circuits

In this paper an NMOS based sinusoidal oscillator is presented. The circuit is constructed with voltage-mode (VM) NMOS-based analog adder and subtractor circuits which respectively perform V1+V2 and V1-V2 operations on the input voltages. The most important feature of the proposed circuits is their extremely simple structures containing only twelve NMOS transistors (six for the adder, six for the subtractor). Another significant advantage of the proposed circuits is that no external passive components are being used. The post-layout simulations of the proposed oscillator circuit have been executed using TSMC 0.25 μm process parameters with ±1.25 V power supply voltage.

CMOS Realization of a Quantized-Output Classifier Circuit

In this paper a CMOS implementation of a multi-input data classifier with several output levels and a different architecture is presented. The proposed circuit operates in current-mode and can classify several types of analog vector data. The classifier circuits new architecture consists of the interconnections of core cells each possessing a current-voltage converter, an inverter followed by a NOR gate and a voltage-current output stage. Using 0.35 mum TSMC technology parameters, SPICE simulation results for a classifier with two inputs are included to verify the expected results.