J.A. Hutchby

High-performance interconnects: an integration overview

The Information Revolution and enabling era of silicon ultralarge-scale integration (ULSI) have spawned an ever-increasing level of functional integration on-chip, driving a need for greater circuit density and higher performance. While traditional transistor scaling has thus far met this challenge, interconnect scaling has become the performance-limiting factor for new designs. The increasing influence of interconnect parasitics on crosstalk noise and R(L)C delay as well as electromigration and power dissipation concerns have stimulated the introduction of low-resistivity copper and low-permittivity (k) dielectrics to provide performance and reliability enhancement. Integration of these new materials into integrated circuit fabrication is a formidable task, requiring material, process, design, and packaging innovations. Additionally, entirely new technologies such as RF and optical interconnects may be required to address future global routing needs and sustain performance improvement.

Growth and diffusion of abrupt zinc profiles in gallium arsenide and heterojunction bipolar transistor structures grown by organometallic vapor phase epitaxy

The growth and diffusion of abrupt Zn profiles in undoped gallium arsenide (GaAs), silicon‐doped GaAs, and heterojunction bipolar transistor structures grown by organometallic vapor phase epitaxy have been studied using secondary ion mass spectrometry depth profiling. The depth profiles indicate that abrupt (within 100 A) turn‐on of Zn doping to levels approaching 1020 cm−3 are obtainable, while abrupt turn‐off is limited to about two orders of magnitude due to dopant tailing toward the surface resulting from residual Zn in the reactor. The sharp diffusion fronts resulting from post‐growth anneals indicate that the Zn diffusion coefficient has a concentration dependence. However, the diffusion of Zn at high concentrations appears to be inhibited by crystal defect kinetics resulting in a relatively concentration‐independent Zn diffusion coefficient. The V/III growth ratio did not have an effect on Zn diffusion in undoped or silicon‐doped GaAs. The diffusion of Zn in heterojunction bipolar transistor struct...

18.2% (AM1.5) efficient GaAs solar cell on optical-grade polycrystalline Ge substrate

In this work, the authors present GaAs material and device-structure optimization studies that have led to achieve a open-circuit voltage of /spl sim/1 volt and a best solar cell efficiency of 18.2% under AM1.5G illumination, for a 4 cm/sup 2/ area GaAs cell on commercially-available, cast, optical-grade polycrystalline Ge substrate. This V/sub /spl infin// is almost 70 mV higher than on their previously-reported best GaAs cell on similar substrates. They discuss the growth of high-quality GaAs-AlGaAs layers, across the various crystalline orientations of a polycrystalline Ge substrate, important for obtaining good device performance. Optimization studies of the minority-carrier properties of GaAs layers on poly-Ge substrates have revealed that lifetime-spread across various grains can be reduced through the use of lower doping for the Al/sub 0.8/Ga/sub 0.2/As confinement layers. The cell-structure optimization procedures for improved V/sub /spl infin// and cell efficiency, include the use of thinner emitters, a spacer layer near the p/sup +/-n junction and an improved window layer. An experimental study of dark currents in these junctions, with and without the spacer, as a function of temperature (77 K to 288 K) is presented indicating that the spacer reduces the tunneling contribution to dark current.

High-performance p-n-p AlGaAs/GaAs heterojunction bipolar transistors: A theoretical analysis

The AlGaAs/GaAs P-n-p heterojunction bipolar transistor (HBT) is shown by a simple analysis to exhibit millimeter wave and digital switching performance comparable to similar N-p-n structures. For example, a P-n-p HBT with a 1-µm emitter stripe and 34-µm²total area yields<tex>f_{\tau} = 31</tex>GHz,<tex>f_{\max} = 94</tex>GHz, and an intrinsic switching speed<tex>\tau_{s} = 8</tex>ps. A similar N-p-n structure exhibits<tex>f_{\tau} = 56</tex>GHz,<tex>f_{\max} = 102</tex>GHz, and<tex>\tau_{s} = 8</tex>ps.

Visible light emission from quantized planar Ge structures

Visible photoluminescence has been observed near 1.9 eV at 300 K from quantized planar Ge structures. This is the first observation of luminescence in Ge and is similar to the recently reported luminescence from porous Si. The quantum structures are prepared from bulk Ge substrates, and both n‐ and p‐type Ge produce luminescence at room temperature. These structures are fabricated by plasma‐assisted etching using a CF4/O2 gas mixture.

Monolithic integration of complementary HBTs by selective MOVPE

The monolithic integration of n-p-n and p-n-p heterojunction bipolar transistors (HBTs) through the use of selective metal organic vapor phase epitaxial regrowth is discussed. This was accomplished by masking, patterning, and etching a p-n-p HBT wafer and then selectively regrowing an n-p-n structure in the etched areas. The selective epitaxial regrowth did not degrade the current gain of the p-n-p structure. Several complementary amplifier circuits were fabricated and tested successfully, demonstrating the feasibility of a monolithic complementary HBT technology.<<ETX>>

An inverted-growth approach to development of an IR-transparent, high-efficiency AlGaAs/GaAs cascade solar cell

An approach for inverted-grown AlGaAs/GaAs cascade cells, where the AlGaAs top cell is grown first at high temperatures, placing the surface to be illuminated nearest to the substrate, is presented. Following the growth of the top cell, the GaAs tunnel interconnect and the bottom cell are grown at lower temperatures. After the inverted growth, the AlGaAs/GaAs cascade structure is selectively removed from the parent substrate, Ge in this case. Advantages of the inverted-growth approach are discussed.<<ETX>>

Photoluminescence of porous silicon buried underneath epitaxial GaP

Recent observations of visible, room‐temperature photoluminescence in porous Si have stimulated research aimed at the realization of efficient, Si‐based electroluminescent devices. To achieve electroluminescence, it may be beneficial to generate carriers with sufficient energy to populate the states of the quantum‐confined Si structures. A viable method to accomplish this is to utilize a wide‐band‐gap heterojunction injector, such as GaP. Toward that end, we report the successful formation of porous Si buried underneath GaP islands, and we demonstrate that the buried porous Si layer exhibits strong photoluminescence (λ≊7000 A).

Low emitter resistance GaAs based HBT's without InGaAs caps

Low emitter resistance is demonstrated for AlGaAs/GaAs heterojunction bipolar transistors using Pd/Ge contacts on a GaAs contact layer. The contact resistivity to 2-10/spl times/10/sup 18/ cm/sup -3/ n-type GaAs is 4-1/spl times/10/sup -7/ /spl Omega/-cm/sup 2/. These are comparable to contact resistivities obtained with non-alloyed contacts on InGaAs layers. The non-spiking Pd/Ge contact demonstrates thermal stability and area independent resistivity suitable for scaled devices. The substitution of Pd/Ge for AuGe/Ni GaAs emitter and collector contacts reduced by an order of magnitude the emitter-base offset voltage at high current densities and increased f/sub t/ by more than 15% with significantly improved uniformity for devices with 2 and 2.6 /spl mu/m wide emitters having lengths two, four and six times the width.<<ETX>>

Development of 20% efficient GaInAsP solar cells

The authors report on the development of two compositions of a GaInAsP lattice-matched to GaAs for photovoltaic applications. Successful development of cascade solar cells necessitates the development of both high bandgap (1.5 to 1.9 eV) as well as low bandgap (0.7 to 1.4 eV) materials. The GaInAsP lattice-matched to GaAs is an excellent candidate for the high band gap material. Ga/sub 0.84/In/sub 0.16/As/sub 0.68/P/sub 0.32/ cells, with a band gap of 1.55 eV, have been developed that have demonstrated a V/sub oc/ of 1.047 volts, a J/sub sc/ of 22.5 mA/cm/sup 2/, a fill factor of 0.849, and an active area efficiency of 21.8 per cent under AM1.5 direct illumination. A Ga/sub 0.84/In/sub 0.16/As/sub 0.68/P/sub 0.32/ tunnel diode has also been developed with a peak current of 4.33/spl times/102/spl sim/mA/cm/sup 2/ at a voltage of 65 mV. Both the Ga/sub 0.84/In/sub 0.16/As/sub 0.68/P/sub 0.32/ cell and tunnel diode are being used in conjunction with a Ge cell to develop a monolithic Ga/sub 0.84/In/sub 0.16/As/sub 0.68/P/sub 0.32Ge cascade cell. Ga/sub 0.68/In/sub 0.32/As/sub 0.34/P/sub 0.66/ cells, with a band gap of 1.7 eV, have been developed that have demonstrated a V/sub oc/ of 1.161 volts, a J/sub sc/ of 28.9 mA/cm2 a fill factor of 0.86, and an active area efficiency of 21.4 per cent under AMO illumination. The Ga/sub 0.68/In/sub 0.32/As/sub 0.34/P/sub 0.66/ cells have also demonstrated resistance to radiation damage as well as a recovery of preirradiation performance after low temperature annealing.<<ETX>>