George I. Bourianoff

Extending the road beyond CMOS

The accelerating pace of CMOS scaling is rapidly approaching the fundamental limits of MOSFET performance, even as the projected size of a high-performance and manufacturable MOSFET technology is currently being extended with growing confidence to the 22-nm node (featuring a 9-nm physical gate length). The new 2001 International Technology Roadmap for Semiconductors currently projects the industry to reach this node in 2016. However, this forecast assumes the traditional industry node-cycle cadence of a quadrupling of the number of transistors every three years for DRAMS and a return to the three-year cycle in 2004 for MPUs and ASICs. During the past several years the node cycles for MPUs have been accelerated to occur within two-year periods. This pace will bring the microelectronics industry to the end of silicon CMOS technology scaling sometime not later than 2016, and maybe as soon as 2010. The new Emerging Technologies section of the 2001 ITRS offers guidance on both sides of this problem: nanoelectronics for memory, logic, and information-processing architectures could possibly extend the time frame of the ITRS beyond CMOS.

Proposal of a Spin Torque Majority Gate Logic

A spin-based logic device is proposed. It is comprised of a common free ferromagnetic layer and four discrete ferromagnetic nanopillars, each containing an independent fixed layer. It has the functionality of a majority gate and is switched via motion of domain walls by spin transfer torque. Validity of its logic operation and a quantitative performance prediction are demonstrated by micromagnetic simulation. It is entirely compatible with complimentary metal-oxide-semiconductor technology.

CMOS-compatible synthesis of large-area, high-mobility graphene by chemical vapor deposition of acetylene on cobalt thin films.

We demonstrate the synthesis of large-area graphene on Co, a complementary metal-oxide-semiconductor (CMOS)-compatible metal, using acetylene (C(2)H(2)) as a precursor in a chemical vapor deposition (CVD)-based method. Cobalt films were deposited on SiO(2)/Si, and the influence of Co film thickness on monolayer graphene growth was studied, based on the solubility of C in Co. The surface area coverage of monolayer graphene was observed to increase with decreasing Co film thickness. A thorough Raman spectroscopic analysis reveals that graphene films, grown on an optimized Co film thickness, are principally composed of monolayer graphene. Transport properties of monolayer graphene films were investigated by fabrication of back-gated graphene field-effect transistors (GFETs), which exhibited high hole and electron mobility of ∼1600 cm(2)/V s and ∼1000 cm(2)/V s, respectively, and a low trap density of ∼1.2 × 10(11) cm(-2).

The future of nanocomputing

We are aware that the semiconductor industry had already entered the nanotechnology world. The working group proposed a hierarchy consisting of four levels: devices, architecture, state variables and data representation. We review on 3D heterogeneous integration, quantum cellular automata, defect-tolerant architecture, quantum computing, nano devices and other novel devices. This experience suggests some criteria we will need to apply to bring these early research efforts into the realm of high-volume manufacturing.

Silicon optical nanocrystal memory

We describe the operation of a silicon optical nanocrystal memory device. The programmed logic state of the device is read optically by the detection of high or low photoluminescence intensity. The suppression of excitonic photoluminescence is attributed to the onset of fast nonradiative Auger recombination in the presence of an excess charge carrier. The device can be programmed and erased electrically via charge injection and optically via internal photoemission. Photoluminescence suppression of up to 80% is demonstrated with data retention times of up to several minutes at room temperature.

CMOS supporting circuitries for nano-oscillator-based associative memories

“Let physics do computing” is a promising approach to new-paradigm computing in the beyond CMOS era. Building associative memories based on the physics of nano oscillators, in particular, presents a lot of potential for intelligent information processing. In this paper, we discuss how CMOS supporting circuitries can interface the fabric of nano oscillators with digital computing world. Using CMOS ring oscillators to emulate the nano oscillator behavior, how to produce the associative memory function and to use it for image recognition is demonstrated by HSPICE simulation.

Non-Boolean associative architectures based on nano-oscillators

Many of the proposed and emerging nano-scale technologies simply cannot compete with CMOS in terms of energy efficiency for performing Boolean operations. However, the potential for these technologies to perform useful non-Boolean computations remains an opportunity to be explored. In this talk we examine the use of the resonance of coupled nano-scale oscillators as a primitive computational operator for associative processing and develop the architectural structures that could enable such devices to be integrated into mainstream applications.

Emerging Nanoscale Memory and Logic Devices: A Critical Assessment

This article presents the ERD Working Groups collective judgment with respect to the long-term potential of nanoscale memory and logic devices to replace silicon-based CMOS logic or baseline memory technology. It does not judge their potential to supplement or complement CMOS. The intent is thus prescriptive, not prescriptive: to provide a technically grounded, objective benchmark for emerging research memory and logic devices.

Coupled-Oscillator Associative Memory Array Operation for Pattern Recognition

The operation of an array of coupled oscillators underlying the associative memory function is demonstrated for various interconnection topologies (cross-connect and star-coupled). Three types of nonlinear oscillators (Andronov-Hopf, phase-locked loop, and spin torque) and their synchronization behavior are compared. Frequency-shift keying scheme of encoding input and memorized data is introduced. The speed of synchronization of oscillators and the evolution of the degree of match are studied as a function of device parameters.

Strategies and tolerances of spin transfer torque switching

Schemes of switching memories based on magnetic tunnel junctions via the effect of spin torque with various polarizations of injected electrons are studied. Simulations based on macrospin and micromagnetic theories without account of thermal fluctuations are performed and compared. We demonstrate that short-pulse precessional switching with perpendicularly polarized current requires a shorter time and smaller energy than switching with collinear in-plane spin polarization. We also show that memory cells based on precessional switching are superior to those in current technologies. We study the dependence of switching on the magnitude of current and pulse duration. An increased Gilbert damping is found to improve tolerances of perpendicular-polarization switching without increasing the threshold current, unlike in-plane switching.