J. B. Choi

Si-based ultrasmall multiswitching single-electron transistor operating at room-temperature

An ultrasmall single-electron transistor has been made by scaling the size of a fin field-effect transistor structure down to an ultimate limiting form, resulting in the reliable formation of a sub-5 nm Coulomb island. The charge stability data feature the first exhibition of three and a half clear Coulomb diamonds at 300 K, each showing a high peak-to-valley current ratio. Its charging energy is estimated to be more than one order magnitude larger than the thermal energy at room-temperature. The hybrid literal gate integrated by this single-electron transistor combined with a field-effect transistor displays >5 bit multiswitching behavior at 300 K with a large voltage swing of ∼1 V.

Room-temperature charge stability modulated by quantum effects in a nanoscale silicon island.

We report on transport measurement performed on a room-temperature-operating ultrasmall Coulomb blockade devices with a silicon island of sub5 nm. The charge stability at 300K exhibits a substantial change in slopes and diagonal size of each successive Coulomb diamond, but remarkably its main feature persists even at low temperature down to 5.3K except for additional Coulomb peak splitting. This key feature of charge stability with additional fine structures of Coulomb peaks are successfully modeled by including the interplay between Coulomb interaction, valley splitting, and strong quantum confinement, which leads to several low-energy many-body excited states for each dot occupancy. These excited states become enhanced in the sub5 nm ultrasmall scale and persist even at 300K in the form of cluster, leading to the substantial modulation of charge stability.

SOI single-electron transistor with low RC delay for logic cells and SET/FET hybrid ICs

We report on a successful fabrication of silicon-based single-electron transistors (SETs) with low RC time constant and their applications to complementary logic cells and SET/field-effect transistor (FET) hybrid integrated circuit. The SETs were fabricated on a silicon-on-insulator (SOI) structure by a pattern-dependent oxidation (PADOX) technique, combined with e-beam lithography. Drain conductances measured at 4.2 K approach large values of the order of microsiemens, exhibiting Coulomb oscillations with peak-to-valley current ratios /spl Gt/1000. Data analysis with a probable mechanism of PADOX yields their intrinsic speeds of /spl sim/ 2 THz, which is within an order of magnitude of the theoretical quantum limit. Incorporating these SETs as basic elements, in-plane side gate-controlled complementary logic cells and SET/FET hybrid integrated circuits were fabricated on an SOI chip. Such an in-plane structure is very efficient in the Si fabrication process, and the side gates adjacent to the electron island could easily control the phase of Coulomb oscillations. The input-output voltage transfer, characteristic of the logic cell, shows an inverting behavior where the output voltage gain is estimated to be about 1.2 at 4.2 K. The SET/FET hybrid integrated circuit consisting of one SET and three FETs yields a high-voltage gain and power amplification with a wide-range output window for driving the next circuit. The small SET input gate voltage of 30 mV is finally converted to 400 mV, corresponding to an amplification ratio of 13.

Long-term electron leakage mechanisms through ONO interpoly dielectric in stacked-gate EEPROM cells

Analyzing the measured shift rate of cell threshold-voltage, we have studied the long-term electron leakage mechanisms through an oxide-nitride-oxide (ONO) interpoly dielectric, which causes reliability problems due to the degradation of the data retention characteristics in the stacked-gate Flash EEPROM devices. The cell threshold-voltage shifts were measured as a function of bake time at various temperatures by the high-temperature accelerated test. Based on the experimental results, a new empirical model was developed and evaluated. It can explain the dominant mechanisms for the spontaneous charge leakage through an ONO interpoly dielectric for the long-term phase. The model clearly shows that cell threshold-voltage shifts during the baking test are caused predominantly by the thermally activated direct-tunneling when electrons, after escaping from the internitride trap-sites near the top oxide of ONO layer by the thermionic emission mechanism, finally tunnel through the thin top oxide to the control gate. This interpretation is strongly supported by the V/sub T/-shift and temperature dependence of the V/sub T/-shift rate, showing that the simulation results are well fit to the experimental data.

Single-electron-based flexible multivalued logic gates

Single-electron transistor (SET)-based multivalued (MV) not-AND (NAND) and not-OR (NOR) logic cells were implemented on a silicon-on-insulator chip. Depending on the ways of connecting two SETs with a field-effect transistor, the voltage transfer characteristics show typical NAND or NOR gate functions for various input voltages, which are binary, MV, and binary-MV mixed. Moreover, the switching functionality of our NAND (NOR) can convert to OR (AND) operation by simply adjusting their initial input voltages. These flexible two-input logic gates are expected to provide four basic arithmetic cells for the SET MV logic gate family.

Single-Electron-Based Flexible Multivalued Exclusive- or Logic Gate

By using two symmetrical sidewall gates, we implemented a Si-based single-electron exclusive- OR (XOR) gate and reported on the first flexible multivalued (MV) functionality. A grayscale contour plot of the output voltages displays alternating high/low values as a function of two single-electron transistor (SET) input voltages. Their voltage transfer characteristics display typical XOR or XNOR gate function depending on input voltages for binary, MV, and binary-MV mixed-modes. This flexible two-input XOR gate, combined with the previously reported NAND/NOR gates, provide three basic arithmetic blocks for the SET-based MV logic gate family.

One electron-based smallest flexible logic cell

A one electron-based operating half-adder, the smallest arithmetic block, has been implemented on silicon-on-insulator structure whose basic element is a nanoscale single-electron transistor (SET) with two symmetrical side-wall gates. Grayscale contour plots of the resulting cell output voltages exhibit the Coulomb blockade-induced periodic alternating high/low features. Their voltage transfer characteristics display typical Sum and Carry-Out functions for binary, multi-valued (MV), and binary-MV mixed input voltages. Moreover, the half-adder function converts into a subtraction mode by adjusting control gates of the SET element. This flexible multi-valued cell provides an arithmetic block for the SET MV logic family of high density integration, operating with ultra-low power.

Formation of a quantum dot in a single-walled carbon nanotube using the Al top-gates

We have fabricated gate-controlled carbon-nanotube single-electron devices by utilizing the line-shaped Al top-gates. A quantum dot is formed in the single-walled carbon nanotube between two Al top-gates fabricated using the electron-beam lithography technique. The deposited top-gates flatten the single-walled carbon nanotube locally and the deformed regions play the role of tunneling barrier, whose potential is controlled by the top-gates. We have also investigated the temperature dependence of the conductance G for the devices with the Al top-gates. The power-law dependence, G∝Tα, is observed at high temperatures. However, the exponent α increases as the barrier potential is enhanced.

Multifunctional Device Using Nanodot Array

We have fabricated a new single-electron device (SED) that has many nanodots. Although SEDs have the great advantages of small size and low power consumption, they should have small dots on the order of a few nanometers, which makes them difficult to fabricate. The proposed device uses many nanodots aligned as an array, on which many gate electrodes are attached so as to couple capacitively to underlying nanodots. Some of the gates are used as input gates of a logic-gate device. The others are control gates that are used to change the logic function of the device, such as from an AND gate to an XOR (exclusive OR) one. The principal operations have been demonstrated using numerical simulations.

Single-Electron Device With Si Nanodot Array and Multiple Input Gates

We have developed a flexible-logic-gate single-electron device (SED) with an array of nanodots. Although the small size of SEDs is highly advantageous, the size of the nanodots inevitably fluctuates, which causes variations in device characteristics. This variability can be eliminated and high device functionality can be obtained by exploiting the oscillatory characteristics and multigate capability of SEDs. We fabricated, on a silicon-on-insulator wafer, a Si nanodot array device with two input gates and a control gate and investigated its basic operation characteristics experimentally. The device was demonstrated to operate as a logic gate providing six important logic functions ( and, or, nand, nor, xor, and xnor), which are obtained by adjusting the control-gate voltage.