n Seop Yu

Macromodeling of single-electron transistors for efficient circuit simulation

In this study, the possibility of compact modeling in single-electron circuit simulation has been investigated. It is found that each Coulomb island in single-electron circuits can be treated independently when the interconnections between single-electron transistors are large enough and a quantitative criterion for this condition is given. It is also demonstrated that, in those situations, SPICE macromodeling of single-electron transistors can be used for efficient circuit simulation. The developed macromodel produces simulation results with reasonable accuracy and with orders of magnitude less CPU time than usual Monte Carlo simulations.

Analytical Threshold Voltage Model Including Effective Conducting Path Effect (ECPE) for Surrounding-Gate MOSFETs (SGMOSFETs) With Localized Charges

On the basis of 2-D potential analysis performed while taking into account the effective conducting path effect, a new analytical model for threshold voltage in cylindrical surrounding-gate MOSFETs (SGMOSFETs) that contain localized charges is presented. From the 2-D Poissons equation based on a parabolic potential approximation, a simple and accurate analytical expression for the threshold voltage is derived. The proposed model is validated using a 3-D device simulator, and good agreement is obtained for various device dimensions and charge distributions. This model can be used to investigate hot-carrier-induced degradation of SGMOSFETs.

Design challenges and solutions for ultra-high-density monolithic 3D ICs

Monolithic 3D ICs (M3D) are an emerging technology that offers an ultra-high-density 3D integration due to the extremely small size of monolithic inter-tier vias. We explore various design styles available in M3D and present design techniques to obtain GDSII-level signoff quality results for each of these styles. We also discuss various challenges facing each style and provide solutions to them.

A SPICE-Compatible New Silicon Nanowire Field-Effect Transistors (SNWFETs) Model

Extraction of carrier mobilities of silicon nanowire FETs (SNWFETs) with Schottky source and drain contacts is performed using a newly developed compact model, which is suitable for efficient circuit simulation. The SNWFET model is based on an equivalent circuit including a Schottky diode model for two metal-semiconductor contacts and a SPICE LEVEL 3 MOSFET model for an intrinsic NW. The Schottky diode model is based on our recently developed Schottky diode model that includes thermionic field emission for reverse bias and thermionic emission mechanism for forward bias. It also includes a new analytical Schottky barrier height model dependent on the gate voltages as well as the drain-source voltages. The results simulated from the SNWFET model reproduce various, previously reported experimental results within 10% errors. The mobilities extracted from our model are compared with the mobility calculated without considering the Schottky contacts.

Single-Electron-Based Flexible Multivalued Exclusive- or Logic Gate

By using two symmetrical sidewall gates, we implemented a Si-based single-electron exclusive- OR (XOR) gate and reported on the first flexible multivalued (MV) functionality. A grayscale contour plot of the output voltages displays alternating high/low values as a function of two single-electron transistor (SET) input voltages. Their voltage transfer characteristics display typical XOR or XNOR gate function depending on input voltages for binary, MV, and binary-MV mixed-modes. This flexible two-input XOR gate, combined with the previously reported NAND/NOR gates, provide three basic arithmetic blocks for the SET-based MV logic gate family.

Subthreshold Degradation of Gate-all-Around Silicon Nanowire Field-Effect Transistors: Effect of Interface Trap Charge

We measured and analyzed the subthreshold degradation of the gate-all-around (GAA) silicon nanowire field-effect transistors with the length of 300/500 nm and the radius of 5 nm. An analytical model incorporating the effect of interface traps quantitatively explained the measured subthreshold swing (SS) degradation. A simple electrostatic argument showed that the GAA device had smaller degradation of SS values than planar devices for the same interface trap densities.

Fall-Detection Algorithm Using 3-Axis Acceleration: Combination with Simple Threshold and Hidden Markov Model

Falls are a serious medical and social problem among the elderly. This has led to the development of automatic fall-detection systems. To detect falls, a fall-detection algorithm that combines a simple threshold method and hidden Markov model (HMM) using 3-axis acceleration is proposed. To apply the proposed fall-detection algorithm and detect falls, a wearable fall-detection device has been designed and produced. Several fall-feature parameters of 3-axis acceleration are introduced and applied to a simple threshold method. Possible falls are chosen through the simple threshold and are applied to two types of HMM to distinguish between a fall and an activity of daily living (ADL). The results using the simple threshold, HMM, and combination of the simple method and HMM were compared and analyzed. The combination of the simple threshold method and HMM reduced the complexity of the hardware and the proposed algorithm exhibited higher accuracy than that of the simple threshold method.

One electron-based smallest flexible logic cell

A one electron-based operating half-adder, the smallest arithmetic block, has been implemented on silicon-on-insulator structure whose basic element is a nanoscale single-electron transistor (SET) with two symmetrical side-wall gates. Grayscale contour plots of the resulting cell output voltages exhibit the Coulomb blockade-induced periodic alternating high/low features. Their voltage transfer characteristics display typical Sum and Carry-Out functions for binary, multi-valued (MV), and binary-MV mixed input voltages. Moreover, the half-adder function converts into a subtraction mode by adjusting control gates of the SET element. This flexible multi-valued cell provides an arithmetic block for the SET MV logic family of high density integration, operating with ultra-low power.

Double-dot-like charge transport through a small size silicon single electron transistor

We report double dot like charge transport in a Si single electron transistor with a single fabricated dot. Detailed analysis of the transport data suggests the existence of another quantum dot with a size much larger than the fabricated dot. More importantly, it is shown that the Coulomb oscillations observed at high temperature clearly originate from the fabricated dot. Possible origin of the accidental formation of the second quantum dot is either a defect at the Si=buried oxide interface or a defect in the thermal oxide surrounding the Si quantum wire. ? 2002 Elsevier Science B.V. All rights reserved.

Full-Range Analytic Drain Current Model for Depletion-Mode Long-Channel Surrounding-Gate Nanowire Field-Effect Transistor

A full-range analytic drain current model for depletion-mode long-channel surrounding-gate nanowire field-effect transistor (SGNWFET) is proposed. The model is derived from the solution of the 1-D cylindrical Poisson equation which includes dopant and mobile charges, by using the Pao-Sah gradual channel approximation and the full-depletion approximation. The proposed model captures the phenomenon of the bulk conduction mechanism in all regions of device operation (subthreshold, linear, and saturation regions). It has been shown that the continuous model is in complete agreement with the numerical simulations.