J. Ban

Design and Implementation of the New D0 Level-1 Calorimeter Trigger

Increasing luminosity at the Fermilab Tevatron collider has led the D0 collaboration to make improvements to its detector beyond those already in place for Run IIa, which began in March 2001. One of the cornerstones of this Run IIb upgrade is a completely redesigned level-1 calorimeter trigger system. The new system employs novel architecture and algorithms to retain high efficiency for interesting events while substantially increasing rejection of background. We describe the design and implementation of the new level-1 calorimeter trigger hardware and discuss its performance during Run IIb data taking. In addition to strengthening the physics capabilities of D0, this trigger system will provide valuable insight into the operation of analogous devices to be used at LHC experiments.

A radiation-hard dual channel 4-bit pipeline for a 12-bit 40 MS/s ADC prototype with extended dynamic range for the ATLAS Liquid Argon Calorimeter readout electronics upgrade at the CERN LHC

The design of a radiation-hard dual-channel 12-bit 40 MS/s pipeline ADC with extended dynamic range is presented, for use in the readout electronics upgrade for the ATLAS Liquid Argon Calorimeters at the CERN Large Hadron Collider. The design consists of two pipeline A/D channels with four Multiplying Digital-to-Analog Converters with nominal 12-bit resolution each. The design, fabricated in the IBM 130 nm CMOS process, shows a performance of 68 dB SNDR at 18 MHz for a single channel at 40 MS/s while consuming 55 mW/channel from a 2.5 V supply, and exhibits no performance degradation after irradiation. Various gain selection algorithms to achieve the extended dynamic range are implemented and tested.

Radiation qualification of the front-end electronics for the readout of the ATLAS liquid argon calorimeters

The ATLAS detector has been built to study the reactions produced by the Large Hadron Collider (LHC). ATLAS includes a system of liquid argon calorimeters for energy measurements. The electronics for amplifying, shaping, sampling, pipelining, and digitizing the calorimeter signals is implemented on a set of front-end electronic boards. The front-end boards are installed in crates mounted between the calorimeters, where they will be subjected to significant levels of radiation during LHC operation. As a result, all components used on the front-end boards had to be subjected to an extensive set of radiation qualification tests. This paper describes radiation-tolerant designs, radiation testing, and radiation qualification of the front-end readout system for the ATLAS liquid argon calorimeters.

Elsevier : A radiation-hard dual-channel 12-bit 40 MS/s ADC prototype for the ATLAS liquid argon calorimeter readout electronics upgrade at the CERN LHC

Abstract The readout electronics upgrade for the ATLAS Liquid Argon Calorimeters at the CERN Large Hadron Collider requires a radiation-hard ADC. The design of a radiation-hard dual-channel 12-bit 40xa0MS/s pipeline ADC for this use is presented. The design consists of two pipeline A/D channels each with four Multiplying Digital-to-Analog Converters followed by 8-bit Successive-Approximation-Register analog-to-digital converters. The custom design, fabricated in a commercial 130xa0nm CMOS process, shows a performance of 67.9xa0dB SNDR at 10xa0MHz for a single channel at 40xa0MS/s, with a latency of 87.5xa0ns (to first bit read out), while its total power consumption is 50xa0mW/channel. The chip uses two power supply voltages: 1.2 and 2.5xa0V. The sensitivity to single event effects during irradiation is measured and determined to meet the system requirements.