Peter R. Kinget

Device mismatch and tradeoffs in the design of analog circuits

Random device mismatch plays an important role in the design of accurate analog circuits. Models for the matching of MOS and bipolar devices from open literature show that matching improves with increasing device area. As a result, accuracy requirements impose a minimal device area and this paper explores the impact of this constraint on the performance of general analog circuits. It results in a fixed bandwidth-accuracy-power tradeoff which is set by technology constants. This tradeoff is independent of bias point for bipolar circuits whereas for MOS circuits some bias point optimizations are possible. The performance limitations imposed by matching are compared to the limits imposed by thermal noise. For MOS circuits the power constraints due to matching are several orders of magnitude higher than for thermal noise. For the bipolar case the constraints due to noise and matching are of comparable order of magnitude. The impact of technology scaling on the conclusions of this work are briefly explored.

Integrated GHz Voltage Controlled Oscillators

The voltage controlled oscillator (VCO) is a critical sub-block in communications transceivers. The role of the VCO in a transceiver and the VCO requirements are first reviewed. The necessity of GHz VCOs and the driving factors towards the monolithic integration of the VCO are examined. VCO design techniques are outlined and design trade-offs are explored. The performance of VCOs in different implementation styles is compared to evaluate when and if VCO integration is desirable.

An injection-locking scheme for precision quadrature generation

We describe a novel quadrature splitter based on injection locking a cascade of ring oscillators to a single phase reference clock. The output signals are in accurate quadrature with low phase noise over a wide bandwidth. This scheme operates at a high signal frequency and is inherently insensitive to the shape of the reference clock waveform. Experimental results at 2.7 GHz are reported for a prototype implementation in 0.25µn BiCMOS technology. To prove the viability of this scheme, a single-sideband mixer was implemented along with the splitter. Over many chips, a considerable improvement in sideband rejection was observed from the state of the art.

Low-power programmable gain CMOS distributed LNA

A design methodology for low power MOS distributed amplifiers (DAs) is presented. The bias point of the MOS devices is optimized so that the DA can be used as a low-noise amplifier (LNA) in broadband applications. A prototype 9-mW LNA with programmable gain was implemented in a 0.18-/spl mu/m CMOS process. The LNA provides a flat gain, S/sub 21/, of 8 /spl plusmn/ 0.6dB from DC to 6.2 GHz, with an input impedance match, S/sub 11/, of -16 dB and an output impedance match, S/sub 22/, of -10 dB over the entire band. The 3-dB bandwidth of the distributed amplifier is 7GHz, the IIP3 is +3 dBm, and the noise figure ranges from 4.2 to 6.2 dB. The gain is programmable from -10 dB to +8 dB while gain flatness and matching are maintained.

Impact of transistor mismatch on the speed-accuracy-power trade-off of analog CMOS circuits

The influence of transistor mismatch on the trade-off between speed, accuracy and power consumption of basic building blocks and analog systems is investigated. The ratio (Speed Accuracy/sup 2/)/Power for a circuit or system in CMOS is shown to be only dependent on technological constants which express the matching quality of the technology. Moreover, the minimal power consumption of high speed analog systems in CMOS imposed by transistor mismatch is two orders higher than the limit imposed by thermal noise.

A programmable analog cellular neural network CMOS chip for high speed image processing

A high speed analog image processor chip is presented. It is based on the cellular neural network architecture. The implementation of an analog programmable CNN-chip in a standard CMOS technology is discussed. The control parameters or templates in all cells are under direct user control and are tunable over a continuous value range from 1/4 to 4. This tuning property is implemented with a compact current scaling circuit based on MOS transistors operating in the linear region. A 4/spl times/4 CNN prototype system has been designed in a 2.4 /spl mu/m CMOS technology and successfully tested. The cell density is 380 cells/cm/sup 2/ and the cell time constant is 10 /spl mu/s. The current drain for a typical template is 40 /spl mu/A/cell. The real-time image processing capabilities of the system are demonstrated. From this prototype it is estimated that a 128/spl times/128 fully programmable analog image processing system can be integrated on a single chip using a standard digital submicron CMOS technology. This work demonstrates that powerful high speed programmable analog processing systems can be built using standard CMOS technologies. >

High-frequency distortion analysis of analog integrated circuits

An approach is presented for the analysis of the nonlinear behavior of analog integrated circuits. The approach is based on a variant of the Volterra series approach for frequency domain analysis of weakly nonlinear circuits with one input port, such as amplifiers, and with more than one input port, such as analog mixers and multipliers. By coupling numerical results with symbolic results, both obtained with this method, insight into the nonlinear operation of analog integrated circuits can be gained. For accurate distortion computations, the accuracy of the transistor models is critical. A MOS transistor model is discussed that allows us to explain the measured fourth-order nonlinear behavior of a 1 GHz CMOS upconverter. Further, the method is illustrated with several examples, including the analysis of an operational amplifier up to its gain-bandwidth product. This example has also been verified experimentally.

A 0.5-V 74-dB SNDR 25-kHz Continuous-Time Delta-Sigma Modulator With a Return-to-Open DAC

A 0.5-V third-order one-bit fully-differential continuous-time DeltaSigma modulator is presented. The presented modulator architecture uses true low-voltage design techniques, and does not require internal voltage boosting or low-threshold devices. A return-to-open architecture that enables the ultra-low-voltage realization of return-to-zero signaling for the feedback DAC is proposed. The ultra-low-voltage operation is further enabled by a body-input gate-clocked comparator, and body-input operational transconductance amplifiers for the active-RC loop filter. Fabricated on a 0.18-mum CMOS process, the modulator achieves a peak SNDR of 74 dB in a 25 kHz bandwidth, and occupies an area of 0.6 mm2; the modulator core consumes 300 muW.

A 0.6-V Zero-IF/Low-IF Receiver With Integrated Fractional-N Synthesizer for 2.4-GHz ISM-Band Applications

Supply voltage reduction with process scaling has made the design of analog, RF and mixed mode circuits increasingly difficult. In this paper, we present the design of an ultra-low voltage, low power and highly integrated dual-mode receiver for 2.4-GHz ISM-band applications. The receiver operates reliably from 0.55-0.65 V and is compatible with commercial standards such as Bluetooth and ZigBee. We discuss the design challenges at low voltage supplies such as limited fT for transistors and higher nonlinearities due to limited available signal swing, and present the architectural and circuit level design techniques used to overcome these challenges. The highly integrated receiver prototype chip contains RF front-end circuits, analog baseband circuits and the RF frequency synthesizer and was fabricated in a standard digital 90-nm CMOS process; it achieves a gain of 67 dB, noise figure of 16 dB, IIP3 of -10.5 dBm, synthesizer phase noise of - 127 dBc/Hz at 3-MHz offset, consumes 32.5 mW from 0.6 V and occupies an active area of 1.7 mm2.

Mismatch characterization of small size MOS transistors

A test chip for characterization of transistor mismatch in a standard 1.2 /spl mu/m CMOS technology is presented. A new algorithm for matching parameter extraction has been used. Mismatch parameters based on measurements on 12000 nMOS and 10000 pMOS transistors have been extracted. It is observed that the threshold voltage mismatch linear dependency on the inverse of the square root of the effective channel area no longer holds for transistors of 1.2 /spl mu/m channel length. An extended model based on the physical causes of threshold voltage mismatch is proposed.