J. del Pino

An Analytical Model of Electric Substrate Losses for Planar Spiral Inductors on Silicon

This paper presents a physically based model for estimating the substrate losses due to electric field penetration for planar spiral inductors on silicon not using patterned ground shield. The model, which does not use any fitting parameter, shows excellent agreement with measured data. It has been tested across a variety of inductor geometries and two different substrates up to 10 GHz

Integrated inductors modeling and tools for automatic selection and layout generation

In this work we propose new equivalent circuit models for integrated inductors based on the conventional lumped element model. Automatic tools to assist the designers in selecting and automatically laying-out integrated inductors are also reported. Model development is based on measurements taken from more than 100 integrated spiral inductors designed and fabricated in a standard silicon process. We demonstrate the capacity of the proposed models to accurately predict the integrated inductor behavior in a wider frequency range than the conventional model. Our equations are coded in a set of tools that requests the desired inductance value at a determined frequency and gives back the geometry of the better inductors available in a particular technology.

A novel geometry for circular series connected multilevel inductors for CMOS RF integrated circuits

The scope of this brief is to introduce a novel geometry for circular series connected multilevel inductors. The idea is to improve the overlapping of the different metal layers that form the integrated inductor to maximize the magnetic flux shared by them and so the inductance. The performance of this new geometry has been compared with the conventional one, using Agilent HFSS field solver. After that, two multilevel inductors using this new geometry have been fabricated in a standard 0.6 /spl mu/m three-metal CMOS process and measured.

ON-CHIP INDUCTORS OPTIMIZATION FOR ULTRA WIDE BAND LOW NOISE AMPLIFIERS ¤

In this work, the influence of the inductor quality factor in wide band low noise amplifiers has been studied. Electromagnetic simulations have been used to model the integrated inductor broad band response. The influence of the quality factor on LNA performance of the inductors that compound the impedance matching networks, inductive degeneration and broadband load has been studied, obtaining design guidelines for optimizing the amplifier gain flatness. Using this guidelines, an LNA with wideband input matching, shunt-peaking load, and an output buffer was designed. Using Austria Mikro Systems BiCMOS 0.35 m process, a prototype has been fabricated achieving the following measured specifications: maximum gain of 12.5 dB at 3.4 GHz with a -3 dB bandwidth of 1.7–5.3 GHz, noise figure from 4.3 to 5.2 dB, and unity gain at 9.4 GHz.

Models and Tools for CMOS Integrated Inductors

In this paper we are reporting our research in the development of automatic tools to assist the designers in selecting and automatically laying-out integrated inductors. This task is accomplished by analyzing carefully the lumped equivalent circuit model for these passive components, and using different approaches and modifications depending on the required accuracy and application. As a result modified circuit models for integrated inductors based on the conventional lumped element model are proposed. Model development is based on measurements taken from more than 100 integrated spiral inductors designed and fabricated in a standard silicon process. We show the ability of the proposed models to accurately predict the integrated inductor behavior extending the frequency range where they can be applied as compared with the conventional model.

A Physical-based Method for Parameter Extraction of On-Chip Spiral Inductor

In this work, a new comprehensive method to extract the inductor equivalent model parameters is developed. Frequency-dependent expressions for the model components are obtained from the simplification of the pi-model Y-parameter equations. By analyzing the influence of the components value on the inductor quality factor and inductance, the frequencies at which the parameters will be evaluated are selected. The method has been validated by comparison with measurements of inductors fabricated in a 0.35 mum process. Results show a good agreement over a broad-band frequency up to 10 GHz.

On silicon integrated inductor library design for wireless applications

This contribution reports our research in developing an integrated inductor library. From a tutorial perspective the main limitations of this element, when grown on standard silicon technologies, are presented, offering measured results taken from a set of fabricated inductors and design guidelines to improve their performance. The modeling aspects are also covered, we present results for different equivalent lumped circuits and parameter extraction styles. From the designers point of view, we state the main characteristics that a good integrated inductor library should include. We also report our proposed solution for this task consisting in a set of tools to automate the element selection such as their laying-out. This library development procedure and the associated tools cover the lack of these elements in present offered design kits.

A low-power fully integrated CMOS RF receiver for 2.4-GHz-band IEEE 802.15.4 standard

This paper presents a low power 2.4 GHz receiver front-end for 2.4-GHz-band IEEE 802.15.4 standard in 0.18 μm CMOS technology. This receiver adopts a low-IF architecture and comprises a variable gain single-ended low-noise amplifier (LNA), a quadrature passive mixer, a variable gain transimpedance amplifier (TIA) and a complex filter for image rejection. The receiver front-end achieves 42 dB voltage conversion gain, 10.3 dB noise figure (NF), 28 dBc image rejection and -5 dBm input third-order intercept point (IIP3). It only consumes 5.5 mW.

A Wide-band noise-cancelling CMOS LNA based on Current Conveyors

In this paper, a Wide-band CMOS low-noise amplifier (LNA) based on Current Conveyors (CC) is presented, in which the thermal noise of the input MOSFET is cancelled by exploiting a noise-cancelling technique. This new LNA offers the following notable advantages over existing topologies: wideband performance, with a stable frequency response from 0 to 6.2GHz and wideband input matched impedance with a total absence of passive elements; a low Noise Figure (NF) and high linearity. Comparisons with other topologies prove the effectiveness of the new implementation.

A RF front-end for DVB-SH based on current conveyors

Inductors are used extensively in Radio Frequency Integrated Circuits to design matching networks, load circuits of voltage controlled oscillators, filters, mixers and many other RF circuits. However, on-chip inductors are large and cannot be ported easily from one process to the next. Due to modern CMOS scaling, inductorless RF design is rapidly becoming possible. In this paper a new methodology for designing the RF frontend necessary for the DVB-SH in a 90nm CMOS technology based on the use current conveyors (CC) is presented. The RF frontend scheme is composed of a second generation CC (CCII) LNA with asymmetric input and output, an asymmetric to differential converter, and a passive differential mixer followed by two CCII transimpedance amplifiers to obtain a high gain conversion. Measurements show a conversion gain of 20.8dB, a 14.5dB noise figure, an input return loss (S11) of -14.3dB and an output compression point of -3.9dBm. This combination draws 28.4mW from a ?1.2V supply.