Sunil L. Khemchandani

ON-CHIP INDUCTORS OPTIMIZATION FOR ULTRA WIDE BAND LOW NOISE AMPLIFIERS ¤

In this work, the influence of the inductor quality factor in wide band low noise amplifiers has been studied. Electromagnetic simulations have been used to model the integrated inductor broad band response. The influence of the quality factor on LNA performance of the inductors that compound the impedance matching networks, inductive degeneration and broadband load has been studied, obtaining design guidelines for optimizing the amplifier gain flatness. Using this guidelines, an LNA with wideband input matching, shunt-peaking load, and an output buffer was designed. Using Austria Mikro Systems BiCMOS 0.35 m process, a prototype has been fabricated achieving the following measured specifications: maximum gain of 12.5 dB at 3.4 GHz with a -3 dB bandwidth of 1.7–5.3 GHz, noise figure from 4.3 to 5.2 dB, and unity gain at 9.4 GHz.

Models and Tools for CMOS Integrated Inductors

In this paper we are reporting our research in the development of automatic tools to assist the designers in selecting and automatically laying-out integrated inductors. This task is accomplished by analyzing carefully the lumped equivalent circuit model for these passive components, and using different approaches and modifications depending on the required accuracy and application. As a result modified circuit models for integrated inductors based on the conventional lumped element model are proposed. Model development is based on measurements taken from more than 100 integrated spiral inductors designed and fabricated in a standard silicon process. We show the ability of the proposed models to accurately predict the integrated inductor behavior extending the frequency range where they can be applied as compared with the conventional model.

Wide range fully integrated VCO with new cells-based varactor

This article presents a wide range inductance–capacitance voltage controlled oscillator (VCO) with a unit cells-based varactor. The unit cell represents the minimum possible integrated varactor based on p–n junction diodes, where N+ diffusions are central rectangles, surrounded by doughnut shaped P+ diffusions, with their respective contacts. The varactors are designed using the AMS 0.35 µm BiCMOS process. A physical model has been derived from the measurement of a set of eight fabricated varactors. Measurements indicate that the VCO, which is intended to be used in DVB-H, oscillates from 1.087 to 2.032 GHz, with a 61% tuning range. The phase noises of −124 dBc/Hz at 1 MHz offset and −108 dBc/Hz at 100 kHz offset are obtained.

A Physical-based Method for Parameter Extraction of On-Chip Spiral Inductor

In this work, a new comprehensive method to extract the inductor equivalent model parameters is developed. Frequency-dependent expressions for the model components are obtained from the simplification of the pi-model Y-parameter equations. By analyzing the influence of the components value on the inductor quality factor and inductance, the frequencies at which the parameters will be evaluated are selected. The method has been validated by comparison with measurements of inductors fabricated in a 0.35 mum process. Results show a good agreement over a broad-band frequency up to 10 GHz.

A low-power fully integrated CMOS RF receiver for 2.4-GHz-band IEEE 802.15.4 standard

This paper presents a low power 2.4 GHz receiver front-end for 2.4-GHz-band IEEE 802.15.4 standard in 0.18 μm CMOS technology. This receiver adopts a low-IF architecture and comprises a variable gain single-ended low-noise amplifier (LNA), a quadrature passive mixer, a variable gain transimpedance amplifier (TIA) and a complex filter for image rejection. The receiver front-end achieves 42 dB voltage conversion gain, 10.3 dB noise figure (NF), 28 dBc image rejection and -5 dBm input third-order intercept point (IIP3). It only consumes 5.5 mW.

A Wide-band noise-cancelling CMOS LNA based on Current Conveyors

In this paper, a Wide-band CMOS low-noise amplifier (LNA) based on Current Conveyors (CC) is presented, in which the thermal noise of the input MOSFET is cancelled by exploiting a noise-cancelling technique. This new LNA offers the following notable advantages over existing topologies: wideband performance, with a stable frequency response from 0 to 6.2GHz and wideband input matched impedance with a total absence of passive elements; a low Noise Figure (NF) and high linearity. Comparisons with other topologies prove the effectiveness of the new implementation.

A RF front-end for DVB-SH based on current conveyors

Inductors are used extensively in Radio Frequency Integrated Circuits to design matching networks, load circuits of voltage controlled oscillators, filters, mixers and many other RF circuits. However, on-chip inductors are large and cannot be ported easily from one process to the next. Due to modern CMOS scaling, inductorless RF design is rapidly becoming possible. In this paper a new methodology for designing the RF frontend necessary for the DVB-SH in a 90nm CMOS technology based on the use current conveyors (CC) is presented. The RF frontend scheme is composed of a second generation CC (CCII) LNA with asymmetric input and output, an asymmetric to differential converter, and a passive differential mixer followed by two CCII transimpedance amplifiers to obtain a high gain conversion. Measurements show a conversion gain of 20.8dB, a 14.5dB noise figure, an input return loss (S11) of -14.3dB and an output compression point of -3.9dBm. This combination draws 28.4mW from a ?1.2V supply.

A high sensitivity and low power envelope detector for wireless sensor nodes

In this paper different parts of a wake-up receiver for wireless sensor node are presented. The circuit is composed of an amplifier with input impedance matching network and an envelope detector both working at 868 MHz. The amplifier is incorporated in order to increase the sensitivity of the wake-up receiver. The amplified signal passes to the envelope detector which demodulate on-off keying signal at 125 kHz. The circuits have been designed to optimize power consumption and area. The total power consumption and the minimum signal detected are 44.32 uW and 0.4 mVp respectively. The circuits were implemented in UMC CMOS 65 nm process.

Influence of gate geometry in integrated MOS varactors on accumulation mode for RF

Driven by the many applications that varactors have in RF integrated blocks, this work analyzes the influence of gate geometry (width and length) on integrated accumulation MOS varactors. For this purpose, a number of varactors have been designed and fabricated on a 0.8 mum CMOS standard technology. The most relevant parameters: quality factor, tuning range, and capacitance, are simulated and compared against measurements. Some design considerations are reported.

Analytical models for PN cross varactors

In this paper, models for the capacitance of cross integrated varactors based in the PN junction are presented. Three different approximations are assumed, in order to reproduce the measured results of the capacitance. The relative error with the measured capacitance is under 10% in all cases.