J. Gebelein

An approach to system-wide fault tolerance for FPGAs

This paper deals with the construction of an entire FPGAbased and fault-tolerant computer system spanning all layers of modern computer architecture. This starts with the protection of the fundamental FPGA configuration matrix, continues to the HDL design of multiple hardware components, essentially required to run regular applications on FPGAs, including processor, memory and interfaces and ends up in the implementation of an operating system running radiation hardened software. Joining all these separate layers with their individual approaches to fault tolerance increases the overall radiation susceptibility to a maximum value and enables the use in high-energy physics particle accelerators. The current design phase is shown exemplary for a faulttolerant soft core CPU including validation results.

The CBM Time-of-Flight wall — a conceptual design

Charged hadron identification in the Compressed Baryonic Matter experiment (CBM) is realized via the Time-of-Flight method [1]. For this purpose the CBM-ToF collaboration designed a Time-of-Flight wall composed of Multi-gap Resistive Plate Chambers (MRPCs). Due to the high interaction rate in CBM of 10 MHz the key challenge is the development of high rate MRPCs above 25 kHz/cm2 which become possible after the development of low resistive glass with extremely good quality. In this article we present the actual conceptual design of the ToF-wall which is subdivided in three parts namely the outer wall, the inner wall and the forward zone that are discussed in detail.

An universal read-out controller

Since 2007 we design and develop a ROC (read-out controller) for FAIRs data-acquisition. While our first implementation solely focused on the nXYTER, today we are also designing and implementing readout logic for the GET4 which is supposed to be part of the ToF detector. Furthermore, we fully support both Ethernet and Optical transport as two transparent solutions. The usage of a strict modularization of the Read Out Controller enables us to provide an Universal ROC where front-end specific logic and transport logic can be combined in a very flexible way. Fault tolerance techniques are only required for some of those modules and hence are only implemented there.

Radiation mitigation efficiency of scrubbing on the FPGA based CBM-TOF read-out controller

Ionizing radiation can severely disturb the function of electronic devices, especially SRAM-based electronics such as Field Programmable Gate Arrays (FPGAs). All components which are being mounted in a radiation environment need to be qualified for use at the respective radiation level. The theory of radiation-induced equipment failures is well known and radiation mitigation techniques have been developed. However, when using commercial off-the-shelf electronics, the internal details of electronic circuits are generally not known. Therefore, the effects of radiation and the efficiency of the mitigation techniques need to be experimentally tested before the usage of the respective electronics can be approved. Here we report the result of such a test, which was carried out at the accelerator facility at Forschungszentrum Jülich, Germany, in August 2012. Contrary to previous tests, our intention was not to characterize the chips internal logic cells using a test design which optimized for this purpose. We have evaluated the efficiency of the radiation mitigation technique scrubbing on the logic of an actual operational firmware which is currently being used by the Compressed Baryonic Matter collaboration for readout of high-energy physics detector prototypes. We did not use the particle flux as reference for characterizing the efficiency, instead, we directly counted the induced upset rate in the configuration memory of a second identical device in the beam. The firmware itself was running on a Xilinx Virtex-4 FPGA operating directly in a 2 GeV proton beam at a particle rate in the order of some 107s-1cm-2. Scrubbing has increased the lifespan of the design by almost a factor of 50 and reduced the amount of corrupted data by a factor of 200. Considering this result we can approve the usage of an FPGA-based read-out controller for the CBM-ToF subdetector.

A resilient, flash-free soft error mitigation concept for the CBM-ToF read-out chain via GBT-SCA

The ToF detector read-out chain of the upcoming CBM experiment at FAIR will be equipped with FPGA-based read-out boards (ROBs), which are going to be operated in a radiation environment. Flash-based FPGAs are not an option for this experiment due to their low total ionizing dose limit compared to SRAM-based FPGAs, and therefore the latter is foreseen for the ROBs. Consequently, precautions against soft errors in the configuration memories of the FPGAs need to be taken to keep the chain operational. The proposed approach merges on-chip single upset correction with external intervention for multiple-bit upsets and resets. The external intervention is going to be implemented via the control path of the chain through the GBT-SCA, which offers a JTAG interface, as well as interrupt-capable GPIOs among other features. Thus, the use of the GBT-SCA enables an event-driven configuration upset mitigation concept, while being itself radiation hardened by design. Conventional blind configuration scrubbing would cause a continuous load on the control path, while the selective frame scrubbing reduces this load significantly. The concept has been validated in beamtests conducted at COSY, FZ Juelich, Germany. The concept, the beamtest results and limitations of the implementation are presented and discussed in this paper.

Beamtest results of Lattice LFE2M20E FPGA

This paper presents beamtest data of the Lattice Semiconductor LFE2M20E, a 90nm SRAM FPGA, for use in areas under effects of ionizing radiation. It includes Single Event Effects (SEE) cross-section and maximum Total Ionizing Dose (TID) response. The device was irradiated with protons and heavy ions using particle accelerators at different beam time experiments.

Preparation of COTS TMS570 MCU for use in ionizing radiation environments

This paper deals with development and irradiation test of a dynamic memory scrubbing routine for the CPU-coupled, SRAM-based memory of the commercial off-the-shelf (COTS) TMS570LS3137 microcontroller. The techniques combine hardware/software co-design concepts, resulting in low design complexity, high performance and high reliability at the same time. The algorithm uses the CPU-coupled ECC Error Correction Code (ECC) mechanism to correct Single Bit Upsets (SBU). It has been developed with the objective of using the COTS microcontroller with dual-CPUs in lockstep as part of a particle accelerator Detector Control System (DCS). The major objective of this paper is to present the on-chip dynamic memory scrubbing mechanism, which prevents SBU error accumulation in the SRAM cells, and provide irradiation test results to proof correct functioning. The current implementation successfully corrects SBUs with a mean time of 5.5 milliseconds as concluded from the tests.

A three-dimensional FPGA array beam detector for ionizing radiation experiments

This paper presents the approach of using an array of SRAM-based FPGAs as low-cost translational beam detector in particle accelerator experiments. It benefits from the well known radiation susceptibility of such devices and introduces a per-chip bit-flip readback counter which allows a three-dimensional graphical representation of the spanned detection area. Live translational tracking, logging and flux calculation are feasible features. Only low voltage (5V) as well as a JTAG programmer are required by the detector array. This simplifies the experimental assembly in comparison to common detector electronics like scintillators or gas ionization chambers.

FPGA Fault Tolerance in Particle Physics Experiments

Abstract The behavior of matter in extreme physical conditions is in focus of many high-energy-physics experiments. For this purpose, high energy charged particles (ions) are collided with each other and energy- or baryon densities are created similar to those at the beginning of the universe or to those which can be found in the center of neutron stars. In both cases a plasma of quarks and gluons (QGP) is present, which decomposes to hadrons within a short period of time. At this process, particles are formed, which allow statements about the beginning of the universe when captured by large detectors, but which also lead to the massive occurrence of hardware failures within the detector´s electronic devices. This article is about methods to mitigate radiation susceptibility for Field Programmable Gate Arrays (FPGA), enabling them to be used within particle detector systems to directly gain valid data in the readout chain or to be used as Detector-Control-System (DCS). Zusammenfassung Viele Experimente der Hochenergiephysik haben Untersuchungen des Verhaltens von Materie unter extremen physikalischen Bedingungen zum Inhalt. Zu diesem Zweck werden geladene Teilchen (Ionen) mit hoher Energie zur Kollision gebracht und dabei Energie- oder Baryonendichten erzeugt, die den Bedingungen im frühen Universum kurz nach dem Urknall bzw. die dem Zentrum von Neutronensternen entsprechen; vgl. Compressed Baryonic Matter (CBM) Experiment. In beiden Fällen entsteht ein Plasma aus Quarks und Gluonen (QGP), das innerhalb sehr kurzer Zeit wieder in Hadronen zerfällt. Die dabei freiwerdenden Partikel erlauben es, sofern in Detektoren erfasst, wichtige Aussagen über den Ursprung des Universums und die Struktur der starken Wechselwirkung zu treffen. Sie verursachen andererseits jedoch auch massiv Fehler in der für ihre Erfassung notwendigen Elektronik. In diesem Artikel werden Verfahren beschrieben, wie Feldprogrammierbare Schaltungen (FPGA) toleranter gegen Fehler dieser Art gemacht werden können, sodass sie auch innerhalb von Detektoren zur Auslese von Daten oder als Detektor-Kontroll-System (DCS) Verwendung finden können.