J.I Moon

A 0.4-V, 90

A 0.4-V phase-locked loop (PLL) that has much improved power efficiency is realized in standard 65-nm CMOS. The PLL employs a novel ultralow-voltage charge pump that compensates current mismatch with an active loop filter and produces significantly reduced reference spurs. Its voltage-controlled oscillator (VCO) is designed with the body-bias technique and includes an automatic frequency calibration circuit that provides low VCO gain and wide tuning range. The PLL output frequency can be tuned from 90 to 350 MHz. At 350-MHz output, the PLL consumes 109 μW, which corresponds to the power efficiency of 0.31 mW/GHz.

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We present a 500-MHz, ultra-low-power phase-locked loop (PLL) realized with the near-threshold supply voltage of 0.4 V in 65-nm CMOS technology. Our PLL employs a new charge pump (CP) circuit structure that can greatly reduce CP up/down current mismatch and their variation with voltage-controlled oscillator (VCO) control voltages. The PLL consumes only 127.8 μW, which corresponds to power efficiency of 0.256 mW/GHz.

350-MHz PLL With an Active Loop-Filter Charge Pump

An ultra-low voltage phase-locked loop (PLL) is demonstrated in standard 130-nm CMOS technology. The PLL employs a novel low-voltage charge-pump circuit which compensates current and leakage mismatches that result in suppressed reference spurs. Its voltage-controlled oscillator is realized with supply-regulated active-loop filter. Our PLL occupies 0.014 mm2 and consumes 88 μW at 0.4-V supply for 200-MHz operation.

A 0.4-V, 500-MHz, ultra-low-power phase-locked loop for near-threshold voltage operation.

This paper presents an inductorless 8-Gb/s adaptive passive equalizer with low-power consumption and small chip area. The equalizer has a tunable RC filter which provides high-frequency gain boosting and a limiting amplifier that restores the signal level from the filter output. It also includes a feedback loop which automatically adjusts the filter gain for the optimal frequency response. The equalizer fabricated in 0.18-㎛ CMOS technology can successfully equalize 8-Gb/s data transmitted through up to 50-㎝ FR4 PCB channels. It consumes 6.75 ㎽ from 1.8-V supply voltage and occupies 0.021 ㎟ of chip area.