Kwang-Chun Choi

A 0.4-V, 90

A 0.4-V phase-locked loop (PLL) that has much improved power efficiency is realized in standard 65-nm CMOS. The PLL employs a novel ultralow-voltage charge pump that compensates current mismatch with an active loop filter and produces significantly reduced reference spurs. Its voltage-controlled oscillator (VCO) is designed with the body-bias technique and includes an automatic frequency calibration circuit that provides low VCO gain and wide tuning range. The PLL output frequency can be tuned from 90 to 350 MHz. At 350-MHz output, the PLL consumes 109 μW, which corresponds to the power efficiency of 0.31 mW/GHz.

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A new type of sampling error corrector for a time- to-digital converter (TDC) having a multiphase reference clock and a binary counter is demonstrated. With this corrector, sampling errors caused by asynchronous TDC inputs are corrected without requiring additional counters or reclocking circuits. A TDC having the corrector is implemented in 90-nm CMOS logic technology. It has 13.6-ps/least significant bit resolution and 13-bit input dynamic range. It consumes 18 mW from a 1.2-V supply and occupies a 100 × 210 μm2 chip area.

350-MHz PLL With an Active Loop-Filter Charge Pump

A new mixed-mode binary phase shift keying (BPSK) demodulator is demonstrated using a half-rate bang-bang phase detector commonly used in clock and data recovery (CDR) applications. This demodulator can be used for new home networking applications using already installed CATV lines. A prototype chip realized by 0.18-mum CMOS process can demodulate 622-Mb/s data at 1.4-GHz carrier frequency. At this data rate, the demodulator core consumes 27.5 mW from a 1.8 V power supply while the core chip area is 210 times 150 mum2. The transmission over 20-m CATV line using the prototype chip is successfully demonstrated.

A Time-to-Digital Converter Based on a Multiphase Reference Clock and a Binary Counter With a Novel Sampling Error Corrector

A low-power 1.6-GHz phase-locked loop (PLL) based on a novel supply-regulated voltage-controlled oscillator (SR-VCO) including an active-loop filter (ALF) is realized. In this PLL, an active RC filter is combined with SR-VCO, achieving the advantages of ALF PLL without penalties in power consumption or phase noises. The PLL has measured rms jitter of 4.82 ps, and its core consumes 990 μW from 1-V supply while the chip area is 420 × 570 μm2 including on-chip passive components required for the ALF and the supply regulator.

A 622-Mb/s Mixed-Mode BPSK Demodulator Using a Half-Rate Bang-Bang Phase Detector

This paper reports a 10-Gb/s power and area efficient clock and data recovery circuit implemented in 65-nm CMOS technology. CMOS static circuits are used as much as possible so that the power consumption and the chip area can be minimized. In order to alleviate the supply sensitivity of CMOS static circuits, a supply-regulator is implemented. At 10-Gb/s, the clock and data recovery circuit consumes 5-mW of power and occupies 0.0075mm2 of area.

A 990-

We demonstrated a silicon photonics-wireless interface integrated circuit (IC) realized in 0.25- μ m SiGe bipolar complementary metal-oxide-semiconductor technology, which converts 850-nm optical nonreturn-to-zero data into 60-GHz binary phase-shift keying wireless data. A transmission of 1.6 Gb/s in 60 GHz using the interface IC is successfully demonstrated with the error-free operation achieved at 6-dBm optical input power.

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A mixed-mode high-speed binary phase-shift keying (BPSK) demodulator for IEEE802.15.3c mm-wave wireless personal area network (WPAN) application is realized with 0.18 mum CMOS process. The demodulator core consumes 23.4 mW from 1.8 V power supply while the chip area is 165 times 110 PMZ. The power-consumption is less than that of the conventional BPSK demodulators and the chip-size is smaller. The proposed circuit is verified by 1-meter 60-GHz wireless link tests with 1-Gb/s data.

1.6-GHz PLL Based on a Novel Supply-Regulated Active-Loop-Filter VCO

A mixed-mode QPSK demodulator for 60-GHz wireless personal area network application is demonstrated. The prototype chip realized by 60-nm CMOS process can demodulate up to 4.8-Gb/s QPSK signals at 4.8-GHz carrier frequency. At this carrier frequency, the demodulator core consumes 54 mW from 1.2-V power supply while the chip area is 150 × 150 µm2. Using the fabricated chip, transmission and demodulation of 1.7-GSymbol/s QPSK signal in 60-GHz link is demonstrated.

A 10-Gb/s power and area efficient clock and data recovery circuit in 65-nm CMOS technology

An ultra-low voltage phase-locked loop (PLL) is demonstrated in standard 130-nm CMOS technology. The PLL employs a novel low-voltage charge-pump circuit which compensates current and leakage mismatches that result in suppressed reference spurs. Its voltage-controlled oscillator is realized with supply-regulated active-loop filter. Our PLL occupies 0.014 mm2 and consumes 88 μW at 0.4-V supply for 200-MHz operation.