J.J.M. Zaal

Mechanical Design and Characterization for MEMS Thin-Film Packaging

In this paper, a thin-film packaging approach is developed. It is meant to provide microelectromechanical systems (MEMS) devices with hermetic encapsulation that is sufficiently strong for transfer molding. A flat slab structure supported by columns is considered as basic geometry for the mechanical model. It takes into account both the plate deflection and the stress at the interface with the columns. To verify the model validity, thin-film packages are fabricated using silicon nitride as material for the capping layer. Both high- and low-temperature processes are used to fabricate the packages. The packages differ for the diameter of the columns (from 2 μm to 28 μm), the distances between columns (from 20 μm to 100 μm), and the capping layer thickness (from 3 μm to 7 μm). The packages are tested at different pressures up to 12.5 MPa (125 bar). Failure points agree well with the mechanical model. The largest package fabricated is a square package of 300 μm side length and with four columns (10 μm diameter) in the middle. It withstands a pressure of 10 MPa with a thin SiN capping layer with a thickness of 6 μm. Moreover, the packages are carried through grinding, dicing, and transfer molding, demonstrating that the presented thin-film encapsulation approach is robust enough for commercial first-level packaging.

Correlating Drop Impact Simulations With Drop Impact Testing Using High-Speed Camera Measurements

The increased use of mobile appliances in todays society has resulted in an increase of reliability issues related to drop performance. Mobile appliances are dropped multiple times during their lifespan and the product is required to survive common drop accidents. The use of lead-free solder compositions and the decreasing size of microelectronics aggravated the sensitivity of these products towards drop failures. Also, the use of miniature IC packages like Wafer Level Chip Scale Packages (WLCSP) with smaller lead sizes resulted in a decreased amount of material available to absorb the loading caused by a drop. A widely accepted method to assess the drop reliability of microelectronics on board-level is the drop impact test. The drop impact test has been standardized by international councils like JEDEC and is widely adopted throughout the industry. The intention of the drop test is to assess the overall product reliability towards dropping, focusing on the solder interconnections. These solder interconnections are usually the first link in the chain to fail. Clearly the drop impact reliability of a product is also influenced by numerous design factors like material compositions, ball layout and product size as well as manufacturing conditions. Solder loading is investigated in this research by using high-speed camera recordings of several drop impact tests with verified Finite Element models. These simulation models are developed in order to gain an insight on the loading pattern of solder joints based on product specifications, interconnect layout and drop conditions prior to physical prototyping. Deflections and frequencies during drop testing are measured using a high-speed camera setup. The high-speed camera experiments are performed on two levels: product level (with different levels of energy and different pulse times) and machine level (rebounds with and without a catcher). Parametric (dynamic and quasi static) 3D models are developed to predict the drop impact performance. The experimental results are used to verify and enhance the simulation models, e.g. by tuning the damping parameters. As a result, the verified models can be used to determine the location of the critical solder joint and to obtain estimates of the solder lifetime performance.

Solder interconnect reliability under drop impact loading conditions using High-speed Cold Bump Pull

Abstract The use of microelectronic components in mobile appliances is constantly increasing. Appliances like mobile phones, PDA’s and navigation systems contain more and more functionality and smaller microelectronic components. Dropping an appliance during its lifespan is very common and the product is required to survive this. The drop however, generates significant forces and vibrations on the internal assembly of the product. The performance of a microelectronic component under drop conditions has thus become an important reliability parameter. Assessing the solder interconnect quality by means of drop impact testing, as standardized by e.g. JEDEC, during normal production requires considerable amounts of time and effort. Besides this, the repeatability of the drop impact test is low and introduces elaborate and time-consuming analysis of the results after testing. Already many researchers have investigated new test techniques capable of replacing the drop impact test. In the CBP test the solder bump is pulled in vertical direction from the die using a small pair of jaws. In this test, by varying the pull speed several different strain rates can be applied to the solder bump. In our research a correlation between the drop impact test and Cold Bump Pull test is investigated. This can be divided into three parts. First by investigating the Cold Bump Pull test apparatus for uncontrolled parameters that might introduce a bias or spread in the results. Secondly by means of modeling the Cold Bump Pull test to investigate solder bump deformation and solder bump loading during pull off. Finally in a comparison the differences and similarities between the two tests are briefly discussed and some observations concerning the solder joint performance are presented.

Correlating drop impact simulations with drop impact testing using high-speed camera measurements

The increased use of mobile appliances in todays society has resulted in an increase of reliability issues related to drop performance. Mobile appliances are dropped multiple times during their lifespan and the product is required to survive common drop accidents. The use of lead-free solder compositions and the decreasing size of microelectronics aggravated the sensitivity of these products towards drop failures. Also, the use of miniature IC packages like Wafer Level Chip Scale Packages (WLCSP) with smaller lead sizes resulted in a decreased amount of material available to absorb the loading caused by a drop. A widely accepted method to assess the drop reliability of microelectronics on board-level is the drop impact test. The drop impact test has been standardized by international councils like JEDEC and is widely adopted throughout the industry. The intention of the drop test is to assess the overall product reliability towards dropping, focusing on the solder interconnections. These solder interconnections are usually the first link in the chain to fail. Clearly the drop impact reliability of a product is also influenced by numerous design factors like material compositions, ball layout and product size as well as manufacturing conditions. Solder loading is investigated in this research by using high-speed camera recordings of several drop impact tests with verified Finite Element models. These simulation models are developed in order to gain an insight on the loading pattern of solder joints based on product specifications, interconnect layout and drop conditions prior to physical prototyping. Deflections and frequencies during drop testing are measured using a high-speed camera setup. The high-speed camera experiments are performed on two levels: product level (with different levels of energy and different pulse times) and machine level (rebounds with and without a catcher). Parametric (dynamic and quasi static) 3D models are developed to predict the drop impact performance. The experimental results are used to verify and enhance the simulation models, e.g. by tuning the damping parameters. As a result, the verified models can be used to determine the location of the critical solder joint and to obtain estimates of the solder lifetime performance.

Challenges in the Assembly and Handling of Thin Film Capped MEMS Devices

This paper discusses the assembly challenges considering the design and manufacturability of a Wafer Level Thin Film Package in MEMS applications. The assembly processes are discussed. The loads associated with these processes are illustrated and evaluated. Numerical calculations are combined with experimental observations in order to estimate the assembly risks. Our results emphasize the need for concurrent design for assembly.

Designing for reliability using a new Wafer Level Package structure

Abstract Wafer Level Packages are one of the most advanced packaging concepts. It combines the advantages of flip chip with conventional surface mount technologies. In recent years, we have seen a tremendous growth in the application of Wafer Level Packages, both in quantities as well as in the number of products where they are implemented. The technology is, however, not without it is challenges with 1st and 2nd level reliability issues. For instance, the limit on the size of Wafer Level Packages has to do with the 2nd level, or solder bump, reliability. This paper highlights our major research and development results on understanding and enhancing the 1st and 2nd level reliability of Wafer Level Packages using combined experimental and virtual prototyping (thermal, mechanical and thermo-mechanical) techniques. Typical 1st level reliability problems within Wafer Level Packages are cracking of repassivation materials, fatigue of bond over active pads, and cracks within the Under Bump Metalisation. Typical 2nd level problems concern solder fatigue and brittle fractures within the intermetallics. To investigate the physics of failure for these problems, dedicated parametric finite element models are constructed including the thin IC layers. Two structures are explored to their potential reliability benefits, being the traditionally used repassivation structure and a newly developed Bump on Active structure. This so-called BUMA structure makes use of a thick Al buffer layer. By combining the experimental results with reliability prediction models, both structures in terms of 1st and 2nd level reliability performance are explored. Based on the results we have designed and manufactured an improved construction that significantly outperforms current solutions.

An alternative solder interconnect reliability test to evaluate drop impact performance

With the increased use of mobile phones, navigation systems, PDAs, laptops and portable gaming devices the drop reliability of microelectronics has become an important parameter. Assessing the solder interconnect quality by means of drop impact testing, as standardized by e.g. JEDEC, during normal production requires considerable amounts of time and effort. Besides this, the repeatability of the drop impact test is low and introduces elaborate and time-consuming analysis of the results after testing. Already many researchers have investigated new test techniques capable of replacing the drop impact test, e.g. high-speed shear, pull and bending. Among those tests is the High Speed Cold Bump Pull test (HSCBP or CBP). In the CBP test the solder bump is pulled in vertical direction from the die using a small pair of jaws. In this test, by varying the pull speed several different strain-rates can be applied to the solder bump. In our research a correlation between the drop impact test and cold bump pull test is investigated. This can be divided into three parts. First by investigating the cold bump pull test apparatus for uncontrolled parameters that might introduce a bias or spread in the results. Secondly by means of modeling the cold bump pull test to investigate solder bump deformation and solder bump loading during pull off. Finally the differences and similarities between the drop impact test and the cold bump pull test are briefly discussed and some observations concerning the solder joint performance are presented.

Mechanical reliability of MEMS packages

This paper presents our effort to predict reliability problems for MEMS packages. MEMS devices are vulnerable to the external loads subjected to it. As such, MEMS devices need to be protected. Capping the device can generate protections: a piece of silicon is placed on top of it to create a cavity above it. Parametric Finite Element models are combined with dedicated verification experiments to address the reliability of four different capping concepts. The results gain a better understanding of MEMS capping issues, with failure modes as cavity deflection, cap fractures, and moisture penetration.

Verification of drop impact simulations using high-speed camera measurements

The increased use of mobile appliances in todays society has resulted in an increase of reliability issues related to drop performance. A common method to assess the drop performance is the JEDEC specified drop impact test [1]. In this research the solder loading is investigated by means of drop impact simulations and high-speed camera measurements. The measurements are used to enhance the simulations by tuning the damping parameters. This results in models that are replicating the drop impact amplitudes and are thereby capable of determining the critical solder joint.

Failure modes of Wafer Level Thin Film MEMS packages during wafer thinning

An increasing number of semiconductor companies have research programs related to MEMS resonators. This can be explained by the possible wide range of application areas. Many resonators operate in vacuum and sealing of the cavity can be obtained by using a Wafer Level Thin Film Package (WLTFP). To fit the MEMS-die into a small package it needs to be thinned. In this paper the effect of wafer thinning on the WLTFP is investigated by means of simulation and experiments. The effects of tape removal on WLTFPs are simulated in 2 and 3 dimensions using the cohesive zones technique. Necessary adhesive properties of the grinding foil are measured by a grinding tape peeling experiment. In 2D FE simulations damage is included to predict the most likely cracking path.