J. Javier Martínez-Álvarez

Evaluation of stereo correspondence algorithms and their implementation on FPGA

The accuracy of stereo vision has been considerably improved in the last decade, but real-time stereo matching is still a challenge for embedded systems where the limited resources do not permit fast operation of sophisticated approaches. This work presents an evaluation of area-based algorithms used for calculating distance in stereoscopic vision systems, their hardware architectures for implementation on FPGA and the cost of their accuracies in terms of FPGA hardware resources. The results show the trade-off between the quality of such maps and the hardware resources which each solution demands, so they serve as a guide for implementing stereo correspondence algorithms in real-time processing systems.

High Performance Implementation of an FPGA-Based Sequential DT-CNN

In this paper an FPGA-based implementation of a sequential discrete time cellular neural network (DT-CNN) with 3×3 templates is described. The architecture is based on a single pipelined cell which is employed to emulate a CNN with larger number of neurons. This solution diminishes the use of hardware resources on the FPGA and allows the cell to process real time input data in a sequential mode. Highly efficient FPGA implementation has been achieved by manual design based on low level instantiation and placement of hardware primitives. The Intellectual Property Core offers an appropriate tradeoff between area and speed. Our architecture has been developed to assist designers implementing discrete CNN models with performance equivalent to hundreds or millions of neurons on low cost FPGA-based systems.

Design and Implementation of a Highly Parameterised FPGA-Based Skeleton for Pairwise Biological Sequence Alignment

This paper describes a novel architecture for the hardware implementation of non-linear multi-layer cellular neural networks. This makes it feasible to design CNNs with millions of neurons accommodated in low price FPGA devices, being able to process standard video in real time.This paper presents the design and implementation of a generic and highly parameterised FPGA-based skeleton for pairwise biological sequence alignment. The skeleton is parameterised in terms of the sequence symbol type i.e. DNA, RNA, or protein sequences, the sequence lengths, the match score i.e. the score attributed to a symbol match or the penalty attributed to a mismatch or gap, and the matching task. Instances of the skeleton implement the Smith-Waterman and the Needleman-Wunsch algorithms. The skeleton has been captured in the Handel-C language which makes it FPGA-platform-independent. It implements the sequence alignment algorithm in hand using a pipeline of basic processing elements, which are tailored to the supplied parameters. Actual hardware implementations of the Smith-Waterman algorithm for protein sequence alignment achieve speed-ups in excess of 100:1 compared to equivalent standard desktop software implementations.

FPGA-based architecture for the real-time computation of 2-D convolution with large kernel size

Bidimensional convolution is a low-level processing algorithm of interest in many areas, but its high computational cost constrains the size of the kernels, especially in real-time embedded systems. This paper presents a hardware architecture for the FPGA-based implementation of 2-D convolution with medium-large kernels. It is a multiplierless solution based on Distributed Arithmetic implemented using general purpose resources in FPGAs. Our proposal is modular and coefficient independent, so it remains fully flexible and customizable for any application. The architecture design includes a control unit to manage efficiently the operations at the borders of the input array. Results in terms of occupied resources and timing are reported for different configurations. We compare these results with other approaches in the state of the art to validate our approach.

Using Reconfigurable Supercomputers and C-to-Hardware Synthesis for CNN Emulation

The complexity of hardware design methodologies represents a significant difficulty for non hardware focused scientists working on CNN-based applications. An emerging generation of Electronic System Level (ESL) design tools is been developed, which allow software-hardware codesign and partitioning of complex algorithms from High Level Language (HLL) descriptions. These tools, together with High Performance Reconfigurable Computer (HPRC) systems consisting of standard microprocessors coupled with application specific FPGA chips, provide a new approach for rapid emulation and acceleration of CNN-based applications. In this article CoDeveloper, and ESL IDE from Impulse Accelerated Technologies, is analyzed. A sequential CNN architecture, suitable for FPGA implementation, proposed by the authors in a previous paper, is implemented using CoDeveloper tools and the DS1002 HPRC platform from DRC Computers. Results for a typical edge detection algorithm shown that, with a minimum development time, a 10x acceleration, when compared to the software emulation, can be obtained.

Hand-based Interface for Augmented Reality

Augmented reality (AR) is a highly interdisciplinary field which has received increasing attention since late 90s. Basically, it consists of a combination of the real scene viewed by a user and a computer generated image, running in real time. So, AR allows the user to see the real world supplemented, in general, with some information considered as useful, enhancing the users perception and knowledge of the environment. Benefits of reconfigurable hardware for AR have been explored by Luk et al. [4]. However, the wide majority of AR systems have been based so far on PCs or workstations.

D14: FPGA-based implementation of the instantaneous frequency estimation of phonocardiographic signals

Abstract The instantaneous frequency can be used to provide information about how the frequency content of the phonocardiogram signal varies in time, in order to characterize the heart sounds and murmurs. The instantaneous frequency of a signal can be calculated from the discrete Hilbert transform, computed through the moving discrete Hartley transform, which reduces the computation time. To compute in real time the instantaneous frequency, the algorithms have been implemented in a FPGA device, exploiting the high performance and flexibility of reconfigurable hardware. The results obtained from the FPGA show high accuracy in comparison to those computed with Matlab ® .

FPGA Translation of Functional Hippocampal Cultures Structures Using Cellular Neural Networks

Electric stimulation in neural cultures in neural cultures may be used for creating adjacent physical or logical connections in the connectivity graph following Hebb’s Law modifying the neural responses principal parameters. The created biological structure may be used for computing a certain function, however this achieved structure vanished with time as the stimulation stops. A DTCNN architecture, specifically designed for optimum parallel implementation over dedicated hardware, is proposed to emulate the behavior ans structure of the biological neuronal culture. The FPGA circuit can be used as a permanent model and is also intended to facilitate and speed up further experimentation.

A scalable CNN architecture and its application to short exposure stellar images processing on a HPRC

Abstract A CNN-based algorithm for short exposure image processing and an application-specific computing architecture developed to accelerate its execution are presented. Algorithm is based on a flexible and scalable Cellular Neural Networks (CNN) architecture specifically designed to optimize the projection of CNN kernels on a programmable circuit. The objective of the proposed algorithm is to minimize the adverse effect that atmospheric disturbance has on the images obtained by terrestrial telescopes. Algorithm main features are that it can be adapted to the detection of several astronomical objects and it supports multi-stellar images. The implementation platform made use of a High Performance Reconfigurable Computer (HPRC) combining general purpose standard microprocessors with custom hardware accelerators based on FPGAs, to speed up execution time. The hardware/software partitioning and co-design process have been carried out using high level design tools, instead of traditional Hardware Description Languages (HDLs). Results are presented in terms of circuit area/speed, processing performance and output quality.

Hardware implementation of a controller based on neurobiological adaptive models of the human motor-control system

A neural structure has been implemented into a device based on the new trends in hardware integration, for motor-control In multisensorial anthropomorphic robotic systems. This implementation gives a solution to the problem of physic integration of biologically Inspired control hierarchies in a robotic head-arm installation for robotic reaching tasks. The complete architecture has been implemented on an electronic board connected to a PC computer through a PCI interface. The hardware structure consists of two blocks: one for the working phase of the system, and the other for the learning and supervision phase of the system. These two blocks have been implemented with different technologies based on DSP processors and FPGAs. The algorithms implemented on DSPs have the function of updating the neural network on the FPGA, supervising the working of the algorithm implemented on FPGA and introducing corrections when the neural network produces results with little errors. The neural network has been implemented on FPGA and implements spatial-motor transformations of the robotic platform. It is programmed and updated by the supervisor implemented on a DSP processor.