J. K. Wang

Single-Event Charge Collection and Upset in 40-nm Dual- and Triple-Well Bulk CMOS SRAMs

CMOS technologies can be either dual-well or triple-well. Triple-well technology has several advantages compared to dual-well technology in terms of electrical performance. Differences in the ion-induced single-event response between these two technology options, however, are not well understood. This paper presents a comparative analysis of heavy ion-induced upsets in dual-well and triple-well 40-nm CMOS SRAMs. Primary factors affecting the charge-collection mechanisms for a wide range of particle energies are investigated, showing that triple-well technologies are more vulnerable to low-LET particles, while dual-well technologies are more vulnerable to high-LET particles. For the triple-well technology, charge confinement and multiple-transistor charge collection triggers the “Single Event Upset Reversal” mechanism that reduces sensitivity at higher LETs.

Electron-Induced Single-Event Upsets in Static Random Access Memory

We present experimental evidence of single-event upsets in 28 and 45 nm CMOS SRAMs produced by single energetic electrons. Upsets are observed within 10% of nominal supply voltage for devices built in the 28 nm technology node. Simulation results provide supporting evidence that upsets are produced by energetic electrons generated by incident X-rays. The observed errors are shown not to be the result of “weak bits” or photocurrents resulting from the collective energy deposition from X-rays. Experimental results are consistent with the bias sensitivity of critical charge for direct ionization effects caused by low-energy protons and muons in these technologies. Monte Carlo simulations show that the contributions of electron-induced SEU to error rates in the GEO environment depend exponentially on critical charge.

Impact of Technology Scaling on SRAM Soft Error Rates

Soft error rates for triple-well and dual-well SRAM circuits over the past few technology generations have shown an apparently inconsistent behavior. This work compares the heavy-ion induced upset cross-section in 28, 40, and 65 nm dual- and triple-well SRAMs over a wide range of particle LETs. Similar experiments on identical layouts for all these technologies along with 3-D TCAD simulations are used to identify the dominant mechanisms for single-event upsets. Results demonstrate that the well-engineering strongly influence the single-event response of SRAMs. Layout also plays an important role and the combined effects of well-engineering and layout determine the soft-error sensitivity of SRAMs fabricated in advanced technology nodes.

A Hysteresis-Based D-Flip-Flop Design in 28 nm CMOS for Improved SER Hardness at Low Performance Overhead

A novel D-Flip-Flop design using hysteresis to improve single-event hardness with low performance overhead is presented. Layout-aware sensitive area simulations were used to estimate the improvement in cross-section for the proposed hysteresis DFF (HDFF) vs. a standard DFF. A test chip with the standard DFF, HDFF, and the DICE FF was designed in a 28 nm CMOS process and exposed to alpha, neutron, and heavy-ion beams. The HDFF design shows 14× and 3× improvements in the alpha and neutron SER, respectively, compared with a standard DFF.

Influence of supply voltage on the multi-cell upset soft error sensitivity of dual- and triple-well 28 nm CMOS SRAMs

Dual- and triple-well bulk CMOS SRAMs fabricated at the 28-nm node were tested using alpha particles and heavy-ions over a range of supply voltages. Dual-well SRAMs have better Multiple Cell Upset (MCU) cross sections and spread for nominal voltage, while triple-well SRAMs are better for reduced voltages. TCAD simulations show that single-event upset reversal due to charge confinement is responsible for improved soft error rate (SER) performance at low voltage operation for triple-well SRAMs.

Temperature dependence of soft-error rates for FF designs in 20-nm bulk planar and 16-nm bulk FinFET technologies

Alpha particle-induced flip-flop soft-error rates (SER) for 20-nm bulk planar and 16-nm bulk FinFET technologies are characterized over temperature with different supply voltages. Experimental results indicate that the 16-nm FinFET SER changes insignificantly with temperature while the 20-nm planar SER increases by ~2x over the same temperature range. 3D TCAD and circuit-level simulations show changes in single-event transient (SET) pulse width and logic gate delay are the controlling factors, with opposing influences on SER.

High-speed pulsed-hysteresis-latch design for improved SER performance in 20 nm bulk CMOS process

A novel pulsed-latch design using hysteresis that operates similarly to an edge-triggered flip-flop with improved SER performance is presented. Design was implemented along with standard D-flip-flop (D-FF) and DICE flip-flop in a 20 nm CMOS process. Alpha and Neutron SER test results indicate ~26× and ~3× better SER hardness respectively for the pulsed-hysteresis-latch compared to D-FF. The design also benefits from a 25% higher speed and has a low area overhead of ~8% over the D-FF. A typical processor utilizing the pulsed-hysteresis-latch design can benefit from a ~5× overall SER reduction which is shown to be better than targeted DICE-FF based hardening, both in terms of SER reduction and performance penalty.

Contribution of Control Logic Upsets and Multi-Node Charge Collection to Flip-Flop SEU Cross-Section in 40-nm CMOS

Heavy-ion measurements on 40-nm flip-flops indicate pattern dependence of cross-section resulting from local control logic upsets, such as clock nodes. A Monte-Carlo model of the flip-flop, calibrated to the heavy-ion data, is used to analyze the impact of multi-node charge collection within a flip-flop due to a single particle strike. Depending on the nodes that collect charge, multi-node charge collection can either increase or decrease the vulnerability of the cell. For neutrons, the overall effect of such events was found to be a net increase in cross-section by up to 16%.

Effects of charge confinement and angular strikes in 40 nm dual- and triple-well bulk CMOS SRAMs

Heavy-ion induced upsets are compared in dual-well and triple-well 40 nm CMOS SRAMs. Charge confinement in triple-well structures triggers the single-event upset reversal mechanism for high LET particles. Due to upset reversal, high LET ion-hits incident at off-normal angles show a decrease in SER compared to normally-incident ions for triple-well SRAM cells.

Bias Dependence of Single-Event Upsets in 16 nm FinFET D-Flip-Flops

With fabrication processes migrating from planar devices to FinFETs, the differences in physical structure necessitate evaluating the SEU mechanisms of FinFET-based circuits. Since FinFET-based bi-stable circuits have shown better stability at low supply voltages and hence improved power dissipation, it is also necessary to assess the SEU performance over a range of voltages. In this work, the SEU cross section of FinFET-based D-flip-flops was measured with alpha particles, protons, neutrons, and heavy-ions. Results show a strong exponential increase in the SEU rate with reduction in bias for low-LET particles. Technology Computer Aided Design (TCAD) simulations show that the weak variation of collected charge with supply voltage, combined with the standard bias dependence of critical charge, is responsible for this trend.