Bharat L. Bhuva

Charge Collection and Charge Sharing in a 130 nm CMOS Technology

Charge sharing between adjacent devices can lead to increased Single Event Upset (SEU) vulnerability. Key parameters affecting charge sharing are examined, and relative collected charge at the hit node and adjacent nodes are quantified. Results show that for a twin-well CMOS process, PMOS charge sharing can be effectively mitigated with the use of contacted guard-ring, whereas a combination of contacted guard-ring, nodal separation, and interdigitation is required to mitigate the NMOS charge sharing effect for the technology studied

Characterization of Digital Single Event Transient Pulse-Widths in 130-nm and 90-nm CMOS Technologies

The distributions of SET pulse-widths produced by heavy ions in 130-nm and 90-nm CMOS technologies are measured experimentally using an autonomous pulse characterization technique. The event cross section is the highest for SET pulses between 400 ps to 700 ps in the 130-nm process, while it is dominated by SET pulses in the range of 500 ps to 900 ps in the 90-nm process. The increasing probability of longer SET pulses with scaling is a key factor determining combinational logic soft errors in advanced technologies. Mixed mode 3D-TCAD simulations demonstrate that the variation of pulse-width results from the variation in strike location.

On-Chip Characterization of Single-Event Transient Pulsewidths

A new on-chip single-event transient (SET) test structure has been developed to autonomously characterize the widths of random SET pulses. Simulation results show measurement granularity of 900 ps for a 1.5 mum technology and also indicate that the measurement granularity rapidly scales down with technology. Laser tests were used to demonstrate circuit operation on test chips fabricated using a 1.5 mum process. The experimental results indicate pulsewidths varying from about 900 ps to over 3 ns as the laser energy was increased

Single-Event Transient Pulse Quenching in Advanced CMOS Logic Circuits

Heavy-ion broad-beam experiments on a 130 nm CMOS technology have shown anomalously-short single-event transient pulse widths. 3-D TCAD mixed-mode modeling in 90 nm and 130 nm bulk CMOS has identified a mechanism for simultaneous charge collection on proximal circuit nodes interacting in a way as to truncate, or ¿quench,¿ a propagated voltage transient, effectively limiting the observed SET pulse widths at high LET. This quenching mechanism is described and analyzed.

HBD layout isolation techniques for multiple node charge collection mitigation

A three-dimensional (3D) technology computer-aided design (TCAD) model was used to simulate charge collection at multiple nodes. Guard contacts are shown to mitigate the charge collection and to more quickly restore the well potential, especially in PMOS devices. Mitigation of the shared charge collection in NMOS devices is accomplished through isolation of the P-wells using a triple-well option. These techniques have been partially validated through heavy-ion testing of three versions of flip-flop shift register chains.

Analysis of Parasitic PNP Bipolar Transistor Mitigation Using Well Contacts in 130 nm and 90 nm CMOS Technology

Three-dimensional TCAD models are used in mixed- mode simulations to analyze the effectiveness of well contacts at mitigating parasitic PNP bipolar conduction due to a direct hit ion strike. 130 nm and 90 nm technology are simulated. Results show careful well contact design can improve mitigation. However, well contact effectiveness is seen to decrease from the 130 nm to the 90 nm simulations.

Single Event Upsets in Deep-Submicrometer Technologies Due to Charge Sharing

Circuit and 3D technology computer aided design mixed-mode simulations show that the single event upset vulnerability of 130- and 90-nm hardened latches to low linear energy transfer (LET) particles is due to charge sharing between multiple nodes as a result of a single ion strike. The low LET vulnerability of the hardened latches is verified experimentally.

Directional Sensitivity of Single Event Upsets in 90 nm CMOS Due to Charge Sharing

Heavy-ion testing of a radiation-hardened-by-design (RHBD) 90 nm dual interlocked cell (DICE latch) shows significant directional sensitivity results impacting observed cross-section and LET thresholds. 3-D TCAD simulations show this directional effect is due to charge sharing and parasitic bipolar effects due to n-well potential collapse.

Design Techniques to Reduce SET Pulse Widths in Deep-Submicron Combinational Logic

Analysis of 90 nm CMOS SET response quantifies the interaction between charge collection and charge redistribution in a matched-current-drive inverter chain. It is shown that the SET pulse width difference between an n-hit and p-hit is due to parasitic bipolar amplification on the PMOS device. This difference is exploited to optimize transistor sizing and n-well contact layout for SET RHBD in combinational logic.

Comparison of Combinational and Sequential Error Rates for a Deep Submicron Process

It has been predicted that upsets due to Single-Event Transients (SETs) in logic circuits will increase significantly with higher operating frequency and technology scaling. For synchronous circuits manufactured at advanced technology nodes, errors due to single-event transients are expected to exceed those due to latch upsets. Experimental results presented in this paper quantify the contribution of logic errors to the total Soft-Error Rate (SER) for test circuits fabricated in a 40 nm bulk CMOS technology. These results can be used to develop guidelines to assist circuit designers adopt effective hardening strategies to reduce the SER, while meeting performance specifications for high speed logic circuits.