J. Kraiem

Advanced Bulk Defect Passivation for Silicon Solar Cells

Through an advanced hydrogenation process that involves controlling and manipulating the hydrogen charge state, substantial increases in the bulk minority carrier lifetime are observed for standard commercial grade boron-doped Czochralski grown silicon wafers from 250-500 μs to 1.3-1.4 ms and from 8 to 550 μs on p-type Czochralski wafers grown from upgraded metallurgical grade silicon. However, the passivation is reversible, whereby the passivated defects can be reactivated during subsequent processes. With appropriate processing that involves controlling the charge state of hydrogen, the passivation can be retained on finished devices yielding independently confirmed voltages on cells fabricated using standard commercial grade boron-doped Czochralski grown silicon over 680 mV. Hence, it appears that the charge state of hydrogen plays an important role in determining the reactivity of the atomic hydrogen and, therefore, ability to passivate defects.

Doping engineering as a method to increase the performance of purified MG Silicon during ingot crystallisation

This paper presents an overview of significant crystallisation results obtained with purified metallurgical grade silicon in the framework of the French Photosil project.

19% efficiency heterojunction solar cells on Cz wafers from non-blended Upgraded Metallurgical Silicon

Highly purified n-type UMG (“Upgraded Metallurgical”) Silicon is a material with a strong potential for high efficiency low cost solar cells. Compared to p-type Silicon, n-type Silicon is in general less susceptible to lifetime degradation due to residual metal impurities or to light induced degradation due to the Boron-Oxygen complex. In this work a 15kg 6 inch mono-c Cz Silicon ingot has been grown from 100% highly purified UMG Silicon obtained with the PHOTOSIL process. In this feedstock the Boron and Phosphorus concentrations measured by GDMS were found to be 0.3 ppmw and 2 ppmw, respectively. The resulting ingot is n-type, fully mono c1 rystalline and has a resistivity range from 0.2 to 1 ohm.cm. Other impurities, especially metals, were not detectable with the analysis techniques applied (GDMS, ICP-OES). The ingot was cut into 125×125 mm2 pseudo square wafers of 180 micron thickness. A first series of solar cells were processed on these wafers using an industrial hetero-junction process by Roth & Rau. The best solar cell from a batch of 14 had an energy conversion efficiency of 19.0% (compared to an average: 18.6%) under standard testing conditions with a very high Voc of 725mV.. An independent confirmation of these results is pending.

Crystallisation of purified metallurgical silicon

The crystallization of purified metallurgical Silicon often leads to multi crystalline ingots which present regions of strong compensation and an inversion of the polarity type. These effects result from the presence of different dopant atoms, donors and acceptors, in this type of Silicon and their different segregation behavior during the crystallization process. The most commonly found dopant atoms in Silicon, Boron and Phosphorous, have relatively high segregation coefficients with an important difference in their absolute value. As a result, suitable resistivities in the 0.5 to 1.0 Ωcm range are obtained in an important part of the ingot, but at a relatively high compensation ratio. This paper discusses these compensation effects, as observed on upgraded metallurgical Silicon from the PHOTOSIL project [1] and using a new crystallization process and furnace developed by CYBERSTAR and APOLLONSOLAR [2].

Study of porous silicon layer for epitaxial thin film silicon solar cells

This paper deals with the investigation of the restructuration impact of porous silicon (PS) during annealing on epitaxial layers properties. The dependence of surface roughness of porous silicon on the annealing time has been studied by AFM. Two kinds of roughness were observed: at a nanometric scale roughness decreases with annealing time showing a densification of the porous silicon while at a micrometric scale roughness increases with time by the apparition of large craters. This phenomenon is well explained by classical sintering theory. Then epitaxial layers were grown by VPE on porous silicon with different annealing time in order to quantify porous silicon restructuration effect on layers properties. Secco etch revealed that the defect density in VPE layers increases significantly with annealing time. This is confirmed by Hall measurements and diffusion length measurements which decrease with annealing time, these results show that porous silicon restructuration has a significant effect on epitaxial layer crystal quality and their electrical properties.