J. Kuzmik

Power electronics on InAlN/(In)GaN: Prospect for a record performance

We compare basic physical parameters of Al/sub 0.2/Ga/sub 0.8/N-GaN quantum well with In/sub 0.17/Al/sub 0.83/N/GaN and In/sub 0.17/Al/sub 0.83/N/In/sub 0.10/Ga/sub 0.90/N quantum well parameters, respectively. It is shown that in comparison to conventional AlGaN/GaN approach, structures based on InAlN/(In)GaN should exhibit two to three times higher quantum well polarization-induced charge. We use high electron mobility transistors (HEMT) analytical model to calculate InAlN(In)GaN HEMTs drain currents and transconductances. A 3.3 A/mm and 2.2 A/mm drain current was calculated for In/sub 0.17/Al/sub 0.83/N/In/sub 0.10/Ga/sub 0.90/N and In/sub 0.17/Al/sub 0.83/N/GaN HEMTs, respectively. This represents up to 205% current increase if compared with AlGaN/GaN HEMT and a record power performance can be expected for new structures.

Determination of channel temperature in AlGaN/GaN HEMTs grown on sapphire and silicon substrates using DC characterization method

Self-heating effects and temperature rise in AlGaN/GaN HEMTs grown on silicon and sapphire substrates are studied, exploiting transistor DC characterization methods. A negative differential output resistance is observed for high dissipated power levels. An analytical formula for a source-drain current drop as a function of parasitic source resistance and threshold voltage changes is proposed to explain this behavior. The transistor source resistance and threshold voltage is determined experimentally at different elevated temperatures to construct channel temperature versus dissipated power transfer characteristic. It is found that the HEMT channel temperature increases rapidly with dissipated power and at 6 W/mm reaches values of /spl sim/320/spl deg/C for sapphire and /spl sim/95/spl deg/C for silicon substrate, respectively.

InAlN/(In)GaN high electron mobility transistors: some aspects of the quantum well heterostructure proposal

The replacement of the AlGaN barrier layer of the AlGaN/GaN high electron mobility transistors (HEMTs) with InAlN of various In molar fractions is suggested. Internal polarization fields in the InAlN/(In)GaN quantum well are described using analytical formulae. InAlN/(In)GaN HEMTs quantum well free electron densities, transistor open channel drain currents and threshold voltages are calculated for different In molar fractions considering the maximal acceptable strain. It is suggested that 0.08 ≤ x ≤ 0.27 for a 15 nm thick InxAl1−xN barrier or 0 ≤ y ≤ 0.18 for a 5–10 nm thick InyGa1−yN channel can be applied for strain without layer relaxation while the quantum well free electron densities up to 4.6 × 1017 m−2 and the transistor open channel drain currents up to 4.5 A mm−1 can be expected.

Analysis of degradation mechanisms in lattice-matched InAlN/GaN high-electron-mobility transistors

We address degradation aspects of lattice-matched unpassivated InAlN/GaN high-electron-mobility transistors (HEMTs). Stress conditions include an off-state stress, a semi-on stress (with a partially opened channel), and a negative gate bias stress (with source and drain contacts grounded). Degradation is analyzed by measuring the drain current, a threshold voltage, a Schottky contact barrier height, a gate leakage and an ideality factor, an access, and an intrinsic channel resistance, respectively. For the drain-gate bias < 38 V parameters are only reversibly degraded due to charging of the pre-existing surface states. This is in a clear contrast to reported AlGaN/GaN HEMTs where an irreversible damage and a lattice relaxation have been found for similar conditions. For drain-gate biases over 38 V InAlN/GaN HEMTs show again only temporal changes for the negative gate bias stresses; however, irreversible damage was found for the off-state and for the semi-on stresses. Most severe changes, an increase in the intrinsic channel resistance by one order of magnitude and a decrease in the drain current by similar to 70%, are found after the off-state similar to 50 V drain-gate bias stresses. We conclude that in the off-state condition hot electrons may create defects or ionize deep states in the GaN buffer or at the InAlN/GaN interface. If an InAlN/GaN HEMT channel is opened during the stress, lack of the strain in the barrier layer is beneficial for enhancing the device stability.

Transient thermal characterization of AlGaN/GaN HEMTs grown on silicon

We studied a temperature increase and a heat transfer into a substrate in a pulsed operation of 0.5 length and 150 /spl mu/m gate width AlGaN/GaN HEMTs grown on silicon. A new transient electrical characterization method is described. In combination with an optical transient interferometric mapping technique and two-dimensional thermal modeling, these methods determine the device thermal resistance to be /spl sim/70 K/W after 400 ns from the start of a pulse. We also localized the high-electron mobility transistor heat source experimentally and we extracted a thermal boundary resistance at the silicon-nitride interface of about /spl sim/7/spl times/10/sup -8/ m/sup 2/K/W. Thermal coupling at this interface may substantially influence the device thermal resistance.

Gate insulation and drain current saturation mechanism in InAlN/GaN metal-oxide-semiconductor high-electron-mobility transistors

The authors investigate 2μm gate-length InAlN∕GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS HEMTs) with 12nm thick Al2O3 gate insulation. Compared to the Schottky barrier (SB) HEMT with similar design, the MOS HEMT exhibits a gate leakage reduction by six to ten orders of magnitude. A maximal drain current density (IDS=0.9A∕mm) and an extrinsic transconductance (gme=115mS∕mm) of the MOS HEMT also show improvements despite the threshold voltage shift. An analytical modeling shows that a higher mobility of electrons in the channel of the MOS HEMT and consequently a higher number of electrons attaining the velocity saturation may explain the observed increase in gme after the gate insulation.

Technology and Performance of InAlN/AlN/GaN HEMTs With Gate Insulation and Current Collapse Suppression Using Zr

We present the technology and performance of InAlN/AlN/GaN MOS HEMTs with gate insulation and surface passivation using Zr or Hf . About 10-nm-thick high- dielectrics were deposited by MOCVD before the ohmic contact processing. Plasma pretreatment allowed the reduction of the temperature of the ohmic contact annealing at 600degC. The insulation and passivation of 2-m gate-length MOS HEMTs lead to a gate leakage current reduction by four orders of magnitude and a 2.5 increase of the pulsed drain-current if compared with a Schottky barrier (SB) HEMT. A dc characterization shows 110 mS mm transconductance and 0.9 A mm drain--currents that represent improvements in comparison to the similar SB HEMT and that is explained by a mobility-dependent carrier depletion effect.

\hbox{O}_{\bm 2}

We present GaN-based high electron mobility transistors (HEMTs) with a 2-nm-thin InAlN/AlN barrier capped with highly doped n++ GaN. Selective etching of the cap layer results in a well-controllable ultrathin barrier enhancement-mode device with a threshold voltage of +0.7 V. The n++ GaN layer provides a 290-Omega/\square sheet resistance in the HEMT access region and eliminates current dispersion measured by pulsed IV without requiring additional surface passivation. Devices with a gate length of 0.5-mum exhibit maximum drain current of 800 mA/mm, maximum transconductance of 400 mS/mm, and current cutoff frequency fT of 33.7 GHz. In addition, we demonstrate depletion-mode devices on the same wafer, opening up perspectives for reproducible high-performance InAlN-based digital integrated circuits.

or Hf

The influence of annealing on properties of Pt Schottky contacts deposited on the electron cyclotron resonance plasma etched surface of an AlGaN/GaN heterostructure has been investigated. It is found that rapid thermal annealing (450 °C and 40 s in nitrogen gas), performed after metal deposition, allows for the preparation of Schottky contacts with similar or better properties than those obtained on a non-etched surface. This procedure is suitable for the realization of recessed high-quality Schottky contacts of AlGaN/GaN HEMTs.

\hbox{O}_{\bm 2}

Heat removal from III-Nitride-based devices into a substrate depends also on an acoustic coupling at III-Nitride/substrate interface. We investigate thermal boundary resistance (TBR) and its effects on temperature distribution for GaN layers on Si, SiC, or sapphire substrates. Micro-Raman method is used for the investigation of TBR at the GaN/Si interface while the transient interferometric mapping (TIM) method is used for investigation of GaN/SiC and GaN/sapphire systems. Thermal modeling is used to analyze the experimental data. We found TBR to be ∼7×10−8 m2 K/W for GaN/Si and ∼1.2×10−7 m2 K/W for GaN/SiC interfaces. The role of TBR at the GaN/sapphire interface in the poor heat transfer from GaN to substrate is found to be less important. It is suggested that the substrate cooling efficiency may be improved if fewer defects are present at the interface to the GaN epistructure.