J.-L. Ogier

An evaluation of the extrinsic cells number in a memory array using cross-correlation products and deconvolution: an instance of a microelectronics experimental inverse problem

This work is devoted to a new, fast and efficient method of evaluating the number of marginal cells in a non-volatile electrical memory array. This extraction from experimental data is fundamentally an inverse problem. The method proposed here is based on simple cross-correlation functions and de-convoluting operations. With the microelectronics device dimension downscaling, the reliability of non-volatile electrical memory has become crucial and any marginal cell can compromise the functioning of the whole array (containing hundreds of thousands of elementary cells). A specific array called Cell Array Structure Test (CAST) has been developed as a useful characterization tool to statistically study retention and endurance performance with few experimental operations. However, this device cannot easily count the low number of failed cells among hundreds of thousands. That is why we had to develop a mathematical method to extract this major quantity from measurements. This method has been validated on an EEPROM CAST – 0.13 µm technology node, but it is extendable to all memory devices integrated in parallel array and more generally to any electrical measurement done in a similar configuration.

How to improve the silicon nanocrystal memory cell performances for low power applications

In this paper we propose to optimize the 1T silicon nanocrystal (Si-nc) memory cell in order to reduce the energy consumption for low power applications. Optimized Channel Hot Electron Injection (a 4.5V programming window is reached consuming 1nJ) and Fowler-Nordheim programming are analyzed and compared. The tunnel oxide thickness, Si-ncs area coverage and SiN silicon nanocrystals capping layer are adjusted to optimize the data retention and endurance criteria. We present for the first time the endurance characteristics of a Si-nc cell up to 106 cycles with a final programming window of 4V.

Charge loss activation during non-volatiles memory data retention

In this paper we develop a method to study and to activate charge loss in a Non-volatile Memories array. We first detail an original date retention test under gate stress on a simple and statistical tool. Then we present the experimental results we obtained after more than 700h at 85°C and 150°C, for six different gate stress conditions. Finally, we extract the activation energy for the observed charge losses, using to different approaches, leading to a discussion on the extracted values and to perspectives for this work.

Non volatile memory reliability prediction based on oxide defect generation rate during stress and retention tests

This paper shows how Floating Gate (FG) memory cells behavior during retention tests can be predicted relying on static electrical stress tests. Retention tests are usually performed at High or Low Temperature Bake (HTB or LTB respectively) to provide warning of an impending failure of the memory cell capability to store data. Retention tests are very useful to screen out defective cell populations but induce significant test time overhead. To overcome this limitation, a correlation between stress and retention time is established to anticipate retention test results. Moreover, further investigations are made to provide a physical explanation for the correlation. Indeed, it is shown that the same FG memory tunnel oxide traps are activated during electrical stress tests (high electric field) and retention tests (low electric field).

Experimental study to push the Flash floating gate memories toward low energy applications

The problem of energy saving has today a relevant importance, concerning in particular all the portable devices as smart phone, tablet PC, smart card and so on [1]. In order to improve the features of these products, particular attention is paid to energy consumption of Flash cells in memory arrays. In this work we investigated the Flash floating gate (FG) dynamic behavior during the channel hot electron (CHE) programming operation. After this, we propose a solution to optimize the energy consumption. The samples studied in this experimental work are Flash floating gate memory cells (embedded NOR flash process). The ONO inter-poly dielectric stack has an equivalent thickness of 14nm, while the tunnel oxide of 9.5nm is grown on a p-type silicon substrate. We evaluated the variation effect of two important technological parameters: channel doping dose (CDD) and lightly doped drain (LDD) energy implantation.

Improving Flash memory endurance and consumption with ultra-short channel-hot-electron programming pulses

In this paper we propose to modify the pulses classically used during the channel-hot-electron programming phase of a Flash memory and to replace it by a sequence of ultra-short pulses in order to decrease the programming window closure observed during the endurance test. We start this work presenting the other solutions published in literature. Then, we describe our advanced measurement setup and finally we show our experimental results. Furthermore we evaluate the impact of these ultra-short pulses on the current consumption during the programming phase.

Dynamic behavior of silicon nanocrystal memories during the hot carrier injection

In this paper we present the last improvement on programming window and consumption of silicon nanocrystal memory cell (Si-nc). Using a dynamic technique to measure the drain current during the hot carrier injection (HCI) programming operation, we explain the behavior of Flash floating gate (F.G.) and silicon nanocrystal memories. We use TCAD simulations to reproduce the charge diffusion in the nanocrystal trapping layer in order to understand the physical mechanism. Finally experimental results of electrical characterizations are shown using different bias conditions to compare the devices.

Fast extraction of extrinsic cells in a NVM array after retention under gate stress

As NVM technology gains maturity, new application fields emerge, often implying new product requirements, especially at high temperature. The data retention is a key criterion for good reliability cells. Many previous studies have already dealt with the charge leakage but some of them seem to show a leakage through SiO2 tunnel oxide [1] while others seem to show a leakage through ONO [2]. We have already proposed an experimental way to identify the involved paths by biasing the cell during data retention [3]. The applied bias is used to cancel either the electric field across tunnel oxide or across ONO, depending on the sign of this bias.

Retention test and electrical stress correlation to anticipate EEPROM tunnel oxide reliability issues

This paper shows how floating gate memory cells behavior during retention tests can be predicted relying on static stress tests. The electric high-field induced during Write/Erase cycles is mainly responsible for the retention time degradation because it creates intrinsic failures or traps in the EEPROM tunnel oxide [1][2]. EEPROM retention degradation due to the oxide quality impacts directly the EEPROM threshold voltage (VT) distribution by creating extrinsic populations. Indeed, post cycling retention tests [3] show a large tail of bits which erase faster than typical bits. Retention is the length of time an EEPROM can reliably retain data. This test is very useful to screen out defective cells but induces significant test time overhead. To overcome this limitation, a new technique based on stress tests is used to anticipate retention test results.