Arnaud Regnier

Quantum effects influence on thin silicon film capacitor-less DRAM performance

As DRAM integration follows CMOS interest for thin silicon films, we analyze the impact of quantum effects on capacitor-less DRAM based on floating-body effect. Quantum effects significantly reduce the memory effect when silicon film reaches 10nm but their major impact is for thin and undoped silicon film

A new 40-nm SONOS structure based on backside trapping for nanoscale memories

Silicon-on-nothing (SON) devices have been analyzed for the first time in view of nanoscaled nonvolatile memories (NVM) applications. Two reliable steady states have been demonstrated using backside charge trapping in the nitride layer under the channel as a memory effect in a 40-nm gate-length pMOS silicon-oxide-nitride-oxide-silicon device realized with SON technology. Low voltages (/spl sim/3 V) are required for memory operations and a threshold voltage memory window superior to 0.5 V can be achieved. Charge loss mechanism is analyzed and very promising data retention behavior is demonstrated at 125/spl deg/C. This architecture, with a storage node localized under the channel, is exactly the same device that can operate as a high-performance transistor at low voltages and as an NVM cell at higher voltage ranges. A total compatibility between logic and the embedded NVM process is thus insured. In view of high-density memories, the feasibility of 2-bit storage in a longer SON device is also demonstrated.

MM11 based flash memory cell model including characterization procedure

The objective of this paper is to present a flash cell model for static and transient simulations. As a core element of this model, a Philips MOS model (MM11) model has been used coupled with the charge neutrality expression in the structure. The charge neutrality, including the charge trapped in the floating gate, is applied to determine the potential of the floating gate. From the floating gate potential, related to the terminal voltages, the drain current and the different charges present in the cell structure are calculated with the MM11 formulation. This pragmatic model takes into account the different injection mechanism (CHE, CHISEL and FN). Moreover, the characterization procedure developed under ICCAP to extract the MM11 model card as well as the tunnel current parameters is presented. This model has been successfully implemented in ELDO

A new architecture of EEPROM for high density and high reliability application

A concept of dual-control gate EEPROM cell and array architecture are proposed. New programming conditions used for write and erase operations are developed to improve the lifetime of the cell. This approach allows a programming of the cell only by the top of the structure without bias on the drain-bulk or source-bulk junctions. Moreover, compared to the standard FLOTOX EEPROM, the select transistor has been eliminated, thus attaining a single transistor configuration so a high density memory cell. A compact model and 2D numerical simulation show that the basic functions of this cell, namely reading, programming and erasing are possible with a suitable setting of the applied voltages. Scalability and endurance potentiality make this cell interesting for future high-density and high reliability applications.

EEPROM Compact Model with SILC Simulation Capability

The objective of this paper is to present a EEPROM compact model suitable for SILC simulation. The SILC module allows simulating the retention capability of the cell after stress. Test chip array distribution and standard tunnel capacitor are used to extract the SILC module parameters. Thus the extraction procedure is detailed. The description of the complete model is presented. A simulation example is given and validated versus measurements.

Effects of 1064 nm laser on MOS capacitor

This study is driven by the need to improve failure analysis methodologies based on laser/silicon interactions, using the functional response of an integrated circuit to local laser stimulation. Thus, it is mandatory to understand the behavior of elementary devices under laser illumination, in order to model and predict the behavior of more complex circuits. This paper characterizes and analyses effects induced by static photoelectric laser stimulation (1064 nm) on a 90 nm technology metal-oxide-semiconductor (MOS) capacitor. On n-MOS capacitor the laser induces interface traps in the low part of the silicon band-gap, contrary to p-MOS capacitor where it is in the upper half part of the gap. It is also shown that electric stress increases the density of such interface traps.

Leakage paths identification in NVM using biased data retention

Abstract In this paper we propose a way to study leakage paths for electrons during data retention in floating gate non-volatile memories and especially in EEPROM memory cells. We investigate the main leakage paths, through tunnel oxide as well as through the tri-layer stack oxide “oxide/nitride/oxide” (ONO). We used a TCAD simulation of the full EEPROM cell to precisely determine the control gate bias voiding the electric field through ONO or tunnel oxide. Data retention measurements are then performed with simulated bias. We highlight the fact that leakage paths during data retention are different for extrinsic and intrinsic cells. Indeed, extrinsic behavior disappears when voiding electric field across tunnel oxide, showing these cells leak through tunnel oxide, whereas intrinsic behavior is the same whatever the electric field across tunnel oxide, showing charge loss in intrinsic cells is due to another path.

Dynamic power reduction through process and design optimizations on CMOS 80 nm embedded non-volatile memories technology

This paper describes different solutions to decrease dynamic consumption of circuits processed on an embedded non-volatile memories CMOS 80 nm technology. Up to 25 % in dynamic power reduction is demonstrated without degrading performances and static leakages of devices and above all, with full DMR compliancy. Ring oscillator designs are used to estimate the dynamic power gain, comparing new development process (B) to reference process (A) currently in use in manufacturing.

Determination of oxide properties with a new fast tunneling current measurement protocol

Written and erased states of a floating gate Non-Volatile Memory (NVM) cell are obtained by modulating the electric charge contained in its floating gate, which is realized by making electrons transit through the tunnel oxide thanks to Fowler-Nordheim (FN) conduction [1]. An accurate prediction of the ‘write’ and ‘erase’ threshold voltages requires good knowledge about the injection current, which is not an easy task when transient phenomena and oxide degradation are involved. Simple Fowler-Nordheim laws are not adequate to explain the shape of I-V characteristics, especially for positive drain voltages [2], as seen on figure 1, and deep depletion in the drain has been shown to have an impact on erase operations [3].

Non volatile memory reliability prediction based on oxide defect generation rate during stress and retention tests

This paper shows how Floating Gate (FG) memory cells behavior during retention tests can be predicted relying on static electrical stress tests. Retention tests are usually performed at High or Low Temperature Bake (HTB or LTB respectively) to provide warning of an impending failure of the memory cell capability to store data. Retention tests are very useful to screen out defective cell populations but induce significant test time overhead. To overcome this limitation, a correlation between stress and retention time is established to anticipate retention test results. Moreover, further investigations are made to provide a physical explanation for the correlation. Indeed, it is shown that the same FG memory tunnel oxide traps are activated during electrical stress tests (high electric field) and retention tests (low electric field).