J.L. Tecpanecatl-Xihuitl

Pixel-Level Image Fusion Scheme based on Linear Algebra

Image fusion refers to the process of integrating complementary image sources from multiple imaging sensor such that the resulting fused image improves the performance of computational analysis tasks such as segmentation, feature extraction and object recognition. The paper introduces a pixel-level image fusion scheme based on linear algebra. The image fusion process begins by computing the discrete wavelet transform of the source images. Then, the wavelet transform of the images are fused using a feature-based rule. A salient feature may extend to several pixels; therefore, a rule that can include a region of pixels containing it results in a more efficient integration. The fusion rule is based on a measurement of the linear dependency of a small window centered on the pixel under consideration. The linear dependency measurement is the Wronskian determinant that is a simple and rigorous test. The performance assessment of the proposed method is established by using mutual information measurement as well as root mean square error and peak signal to noise ratio. The simulation results show that the proposed method is an efficient approach to image fusion.

VLSI architecture for an object change detector for visual sensors

Object detection is a crucial step in visual surveillance. Traditionally, object detection has been performed purely in software in surveillance systems. The problem of object detection, however, becomes critical in the upcoming wireless visual sensors because of size and power constraints. The need for low-power, small size, hardware implementations is greatly felt. This paper introduces a VLSI architecture for Wronskian change detector (WCD). Object detection is done through background subtraction. WCD offers regularity, low complexity and accuracy as well as global illumination changes independency. WCD can be employed in automated visual surveillance on buildings and adjacent parking lots. WCD replaces each pixel by a vector containing luminance value of the pixel and its surrounding area. A linear dependency test is applied to each vector to determine if a change has occurred. WCD is mapped into a 12-processing element array with a fixed window value of 3/spl times/3. Design of each processing element is discussed in detail. Based on extensive search, no VLSI implementation of WCD has been reported previously.

Real-time VLSI architecture for detection of moving object using Wronskian determinant

Several computer vision applications require reliable object detection. Traditionally detection algorithms have been implemented solely in software. Object detection in upcoming wireless visual sensors has a need of hardware implementation with requirements of low power and small area. This paper introduces a hardware implementation of a real-time change detector based on Wronskian Determinant. This detection algorithm offers regularity, low complexity and accuracy as well as robustness against global illumination changes. The proposed architecture is able to process incoming frames on-the-fly, therefore requiring a small amount of memory. The maximum frame rate is 15 fps, however the implementation is flexible enough to allow analysis of less frames if required. Processing unit consist of a basic processing element implemented in pipeline fashion and adder tree to produce final results. The architecture was implemented using a XCV800 FPGA. The power consumption of the whole system is 121 mW

Low complexity decimation filter for multi-standard digital receivers

This paper proposes a reduction in complexity of decimation filter architectures used in multi-standard digital receivers, using IIR filters implemented as a sum of two all-pass filters. The decimation filter is an important block in devices which want to establish communication using different standards. IIR filters are implemented on specific stages of multistage pipeline/interleaving structures, where high order filters are power consuming and area demanding. Therefore, a major reduction in complexity is obtained. Regularity is an important property of all-pass filters, which can be decomposed on first or second order all-pass transfer functions achieving more efficient implementation. The results presented are implemented in pipeline/interleaving architectures using specific decimation decomposition proposed previously. Reductions of 36%, 77%, and 80% are obtained compared with previous works, where basically these implementations are based on linear phase filters. The decimation filter architecture is simulated using Matlab.

Digital IF decimation filters for 3G systems using pipeline/interleaving architecture

This paper presents efficient of IF decimation filters architecture using pipeline/interleaving (PI) technique in which the amount of multiplications is reduced by 50%. The decimation filters are important blocks in software radio terminals to process different communications standards like GSM, IS-95, and UMTS. These kinds of blocks are needed to process the I, and Q components on the digital down-converter. The proposed architecture is evaluated by MATLAB. This evaluation shows that the proposed structures can be utilized in a multimode fashion. The frequency response of the decimator filter for each standard is analyzed and the frequency response for the decimator filter using Pl architectures is also evaluated. The new architecture offers saving of 50% the amount of multiplications compare to the traditional implementation.

Efficient Mutliplierless Polyphase FIR Filter based on New Distributed Arithmetic Architecture

This paper present an efficient polyphase multiplierless finite impulse response (FIR) architecture based on new distributed arithmetic (NEDA). The polyphase structure is based on the decomposition of the transfer function in subfilters connected in parallel. The multiplications involved on each subfilter are replaced by an adder array implemented by NEDA. These subblocks presents a different distribution of Is and Os on the NEDA matrix compared with the implementation of the filter in a direct form or transposed form. NEDA presents a bottleneck that is reduced by a balance between a larger filter order and a reduced coefficient wordlength size impacting the whole structure with this tradeoff. This new architecture involves a reduced number of adders in their implementation without significant overhead. The results presented are compared with previous approaches showing superior result around of 34% average reduction on the total number of adders. Additionally, the proposed design method for FIR filter is simple.

An architecture for automated scene understanding

This paper presents distributed, automated, scene surveillance architecture. Object detection and tracking is performed by a set of region and object agents. The area under surveillance is divided in several sub-areas. One camera is assigned to each sub-area. A region agent is responsible for monitoring a given sub-area. Background subtraction is first performed on the scene taken by the camera. Based on the foreground mask, the region agent segments the incoming frame and creates object agents dedicated to tracking detected objects. Tracking information and segments are sent to a scene processing unit that analyzed this information and determined if a threat pattern is present at the scene and performed appropriate action.

Design of a power-efficient interleaved CIC architecture for software defined radio receivers

This paper presents a novel, power-efficient architecture for decimation filter which is a critical component in multistandard digital receivers. Cascade integrator comb (CIC) filter is used to reduce high data rate because of its straightforward structure composed of adders and delays. The proposed power reduction is obtained by designing the integrator section as a polyphase structure where each polyphase component operates at reduced frequency. The digital receiver must process the in-phase (I) and quadrature (Q) signals using two similar filters. This structure is modified to process both signals with interleaved techniques. Thus, just one structure is needed to perform this operation over the two signals. Additionally, reduced frequency operation on the new structure allows us to use low power circuit design techniques such as voltage scaling to reduce the power consumption without affecting the performance of the whole structure. Power-intensive multiplications required for the polyphase filter components are replaced by add-and-shift multiplications. Different communication standards such as data networks (Mobitex and Ardis) and cellular networks (GSM, IS-95, and UMTS) are considered in the filter design. The architecture has been designed, and analyzed. Power estimation shows that the new architecture consumes only 15% of the power of the original structure (i.e., a savings of 85%).

Efficient multistage decimation filter using pipeline/interleaving architectures for digital IF receiver

This paper presents an efficient multistage decimation filter using a specific decomposition multistage and pipeline/interleaving technique to reduce the amount of multiplications. The multistage decimator filter is an important block on digital IF receivers for advanced dedicated mobile data technology called Mobitex and Ardis networks. The results are presented and compared with current results in the literature. The frequency response shows that the requirements are reached and the amount of multiplications is highly reduced. In each case, we get results with an improvement of 55% and 45% just in the multistage decimation filter. Additionally, using PI techniques we just need a single filter to process the components I, and Q in the IF digital receiver.

Design and implementation of a surface peak thermal detector algorithm

Tenet architecture is a two-tier sensor network architecture that provides a model to implement more complex algorithms due to incorporation of less resource-restricted nodes. Stargate-class nodes called masters form the upper tier while resource-restricted nodes named motes compose the lower tier. This paper introduces a data fusion scheme for a tenet architecture based on the correlation coefficients between data set extracted from the motes. Each master selects four sentinels to calculate the direction in which an event has been detected, and then uses this data as a base data to calculate the correlation coefficient for the incoming data. The aggregate output is a result of a weighted sum of the data collected from the N sensors. The weights are calculated based on the correlation coefficients. The aggregated output is compared with a linear means square (LMS) estimator based on variance. The proposed scheme achieves good performance.