J.M. Stern

An Ultra-high Speed Public Key Encryption Processor

This paper describes the architecture and design of a public key encryption processor which implements the RSA algorithm with key lengths of512 bits. The chip, which is 6.2 by 4.2 millimetres, has been designed in a 0.7 micron CMOS, silicon on insulator process and has a target clock speed of 15OMHz. It is a self contained subsystem which interfaces directly to standard microprocessors and will be capable of encrypting at rates well in excess of 64k baud (for contractural reasons we are unable, at this time, to disclose the emct speed of operation).

Design and evaluation of an epoxy three-dimensional multichip module

A low-cost, three-dimensional multichip module (MCM) technology provides greatly improved system density and reduced mass over planar packaging technologies. The technology offers a high degree of testability that negates the need for known good die (KGD) procurement. Testing is achieved with very low cost overheads and with no increase in the volume of the module. The technology allows complete, heterogeneous systems to be packaged and interconnected in a single, ultra-dense module. The electrical characteristics of the technology are comparable to standard chip packages. However, the parasitics due to package-to-package interconnects are eliminated. This removes the dominant cause of parasitics, dramatically improving the electrical characteristics. A programmable integrated camera and image processing system has been developed which incorporates a grayscale camera, analog-to-digital conversion, four programmable processors and memory. Utilizing the three-dimensional multichip module technology, the system, which consists of nine chips and 36 discrete components, has an overall volume of 4.77 ml. This is approximately six times more dense than an advanced PCB implementation. The system forms the first stage in the design and manufacture of a portable video communications device. For such applications, low system volume and mass are key attributes. The system demonstrates the potential of the packaging technique for the integration of complete mixed signal systems incorporating sensors and processing. Further developments to the technology will provide increased module density, improved routing capacity, and electrical performance.

Silicon-on-insulator (SOI): A High Performance ASIC Technology

This paper describes the design of a 50,000 gate data encryption chip in a 0.7micron Silicon-on-Insulator CMOS technology and compares it to the same chip &signed in a 0.7 micron bulk CMOS process. The portability between rhe two processes has been carefully considered and the pe@ormance compared. SOI is found toperform50% faster, consume 30% less power and occupy approximately the same area as the bulk device.

Utilizing a low cost 3D packaging technology for consumer applications

This paper demonstrates how a low cost three-dimensional packaging (multichip module-vertical) technology can be utilized to implement systems for consumer applications. In any application where system cost, volume and mass are important, this packaging technique can be advantageous, particularly in the rapidly growing portable electronics industry. To illustrate this we present a general-purpose, low-cost camera and image processing system in the new packaging technology. This can be used in multimedia, surveillance and smart vision applications.

Implementing heterogeneous microsystems in a three-dimensional packaging technology

This paper demonstrates how a low cost three-dimensional packaging technology can be utilised to implement heterogeneous microsystems. Systems which integrate sensors, actuators and signal processing are highly complex and often require custom packaging to maximise their potential. Using a novel multichip module packaging technology, referred to as MCM-V (multichip module-vertical) we have demonstrated that three-dimensional MCMs can be applied in the production of high-density microsystems incorporating sensors, bare die and discrete components. As an example, we describe two microsystems, one of which integrates an image sensor and programmable processing resources.

A High Performance RSA Encryption Processor in SOI and Bulk CMOS Technologies

This paper describes the architecture and design of a public key encryption processor which implements the RSA algorithm with key lengths of 512 bits. The chips, which are 6.2 by 4.2 millimetres and contain 50,000 gates, have been designed in a 0.7 micron CMOS, silicon on insulator process and in a 0.7 micron bulk CMOS process. The chips are functionally identical and each form a self contained subsystem which interfaces directly to standard microprocessors. The design of the two chips was carried out in order to directly compare the two silicon processes. SOI is found to perform 50% faster, consume 30% less power and occupy approximately the same area as the bulk device.