J. Rebollo

A Survey of Wide Bandgap Power Semiconductor Devices

Wide bandgap semiconductors show superior material properties enabling potential power device operation at higher temperatures, voltages, and switching speeds than current Si technology. As a result, a new generation of power devices is being developed for power converter applications in which traditional Si power devices show limited operation. The use of these new power semiconductor devices will allow both an important improvement in the performance of existing power converters and the development of new power converters, accounting for an increase in the efficiency of the electric energy transformations and a more rational use of the electric energy. At present, SiC and GaN are the more promising semiconductor materials for these new power devices as a consequence of their outstanding properties, commercial availability of starting material, and maturity of their technological processes. This paper presents a review of recent progresses in the development of SiC- and GaN-based power semiconductor devices together with an overall view of the state of the art of this new device generation.

High frequency characteristics and modelling of p-type 6H-silicon carbide MOS structures

Abstract This paper presents the high frequency electrical characteristics and modelling of Al/SiO 2 / p -type 6HSiC structures. The oxide was thermally grown under dry conditions. Capacitance and conductance vs bias and frequency measurements have been performed in daylight and exposing the capacitors to u.v. light. The experimental C m - V g and G m - V g characteristics show hysteresis effects, which are more important when the samples are exposed to 254 nm u.v. light. This behaviour can be explained in terms of interface traps. The MOS structure modelling is based on an interface trap model in which the interface trap levels are considered to be continuously distributed in the SiC bandgap and only charge exchange between interface trap levels and the SiC bands is allowed. From this formulation and from the G m - f characteristics, the interface state density and the interface trap time constant have been determined.

Analysis of Clamped Inductive Turnoff Failure in Railway Traction IGBT Power Modules Under Overload Conditions

This paper studies the overload turnoff failure in the insulated-gate bipolar transistor (IGBT) devices of power multichip modules for railway traction. After a detailed experimental analysis carried out through a dedicated test circuit, electrothermal simulations at device level are also presented. The simulation strategy has consisted in inducing a current and temperature mismatch in two IGBT cells. Results show that mismatches in the electrothermal properties of the IGBT device during transient operation can lead to uneven power dissipation, significantly enhancing the risk of failure and reducing the lifetime of the power module. Concretely, simulations qualitatively demonstrate that localized hot-spot formation due to a dynamic breakdown could lead to a second breakdown mechanism.

Long-Term Reliability of Railway Power Inverters Cooled by Heat-Pipe-Based Systems

This paper analyzes the impact of a nonuniform temperature distribution inside insulated-gate bipolar transistor (IGBT) power modules on the reliability of railway power inverters. The interaction between the chosen cooling system (a heat-pipe-based one) and the power module is considered in detail. After showing the experimental setup and thermal conditions, thermal mapping inside the power module is carried out. Then, the effects of the thermal cycles on the constitutive elements of the IGBT module are pointed out when considering a real mission profile. Finally, the experimental results from the thermal cycles are linked to problems on the power-inverter reliability. Concretely, the thermal-grease distribution is analyzed on failed IGBT modules coming from the field, and the solder-delamination pattern observed in IGBT modules after endurance cycling tests is also reported.

Study of novel techniques for reducing self-heating effects in SOI power LDMOS

Abstract Self-heating effects in silicon-on-insulator (SOI) power devices have become a serious problem when the active silicon layer thickness is reduced and buried oxide thickness is increased. Hence, if the temperature of the active region rises, the device electrical characteristics can be seriously modified in steady state and transient modes. In order to alleviate the self heating, two novel techniques which lead to a better heat flow from active silicon layer to silicon substrate through the buried oxide layer in SOI power devices are proposed. No significant changes on device electrical characteristics are expected with the inclusion of the novel techniques. The electro-thermal performance of lateral power devices including the proposed techniques is also presented.

Analysis of hot-carrier degradation in a SOI LDMOS transistor with a steep retrograde drift doping profile

This paper reports the electrical performances of a RF SOI power LDMOS transistor with a retrograde doping profile in the entire drift region. A comparison between retrograde and conventional uniformly doped drift SOI power LDMOS transistors is provide by means of a numerical simulation analysis. The proposed structures exhibit better performances in terms of trapped electron distribution and transconductance degradation with no modification of the breakdown voltage capability. Simulation results show that, at a given bias conditions, the reduction of lateral electric field peak at the silicon surface due to the implementation of the retrograde doping profile accounts for the observed reduction of the hot carrier degradation effect.

IGBT module failure analysis in railway applications

This work reports two different characteristic patterns detected in IGBT chips failed in real operation (railway application) by failure analysis procedures. The analysed chips have been recovered from the rheostatic chopper leg and from the three legs which supplies the traction motor. It is observed that depending on the location and characteristics of the detected default (burn-out spot), this failure can be attributed to a latch-up process or a secondary breakdown mechanism. These results are corroborated with tests at limit, obtaining the same result. Consequently, each failure can be linked to overcurrent (latch-up) or overtemperature (secondary breakdown) events, which makes possible to distinguish between problems coming from driving strategies or thermal issues (uneven temperature distribution inside the module or packaging wear-out).

Theoretical evidence for the kick-out mechanism for B diffusion in SiC

In this letter, we analyze by means of first-principles electronic structure calculations the diffusion of B impurities in 3C-SiC. We find, through molecular dynamics, that substitutional B at a Si lattice site is readily displaced by a nearby Si interstitial by the process known as a kick-out mechanism, in agreement with recent experimental results. This is in contrast to the situation in Si, where B has recently been shown to diffuse via an interstitialcy mechanism.

First-principles study of n-type dopants and their clustering in SiC

We report the results of an ab initio study of N and P dopants in SiC. We find that while N substitutes most favorably at a C lattice site, P does so preferably at a Si site, except in n-doping and Si-rich 3C-SiC. Furthermore, we consider a series of dopant complexes that could form in high-dose implantation, in order to investigate the dopant activation behavior in this limit. We find that all N complexes considered lead to passivation through the formation of a deep level. For P, the most stable aggregate is still an active dopant, while passivation is only observed for complexes with a higher formation energy. We discuss how these results could help in the understanding of the observed experimental high-dose doping and codoping behavior of these species.

The thin SOI TGLDMOS transistor: a suitable power structure for low voltage applications

This paper is addressed to the analysis of the trench gate LDMOS transistor (TGLDMOS) in a thin SOI technology and to investigate its suitability for low voltage power applications. The static and dynamic performances have been extensively analyzed by means of numerical simulations and compared with a conventional thin SOI power LDMOS transistor. The specific on-state resistance of the analyzed TGLDMOS structure is lower than that of the LDMOS counterpart, but the structure design has to be optimized to minimize the added contributions to the parasitic capacitances. In this sense, a modified TGLDMOS is also proposed to reduce the gate–drain capacitance and to increase the frequency capability. The expected electrical performance improvements of both TGLDMOS and modified TGLDMOS power transistors corroborate their suitability for 80 V switching and amplifying applications.