J. Moers

Hall effect measurements on InAs nanowires

We have processed Hall contacts on InAs nanowires grown by molecular beam epitaxy using an electron beam lithography process with an extremely high alignment accuracy. The carrier concentrations determined from the Hall effect measurements on these nanowires are lower by a factor of about 4 in comparison with those measured by the common field-effect technique. The results are used to evaluate quantitatively the charging effect of the interface and surface states.

X-ray Nanodiffraction on a Single SiGe Quantum Dot inside a Functioning Field-Effect Transistor

For advanced electronic, optoelectronic, or mechanical nanoscale devices a detailed understanding of their structural properties and in particular the strain state within their active region is of utmost importance. We demonstrate that X-ray nanodiffraction represents an excellent tool to investigate the internal structure of such devices in a nondestructive way by using a focused synchotron X-ray beam with a diameter of 400 nm. We show results on the strain fields in and around a single SiGe island, which serves as stressor for the Si-channel in a fully functioning Si–metal–oxide semiconductor field-effect transistor.

Selectively Grown Vertical Si p-MOS Transistor with Reduced Overlap Capacitances

Abstract Vertical p-MOS transistors with channel length of 130 nm have been fabricated using selective epitaxial growth (SEG) to define the channel region. The vertical layout offers the advantages of achieving short channel lengths and high integration densities while still using optical lithography to define lateral dimensions. Compared to other vertical concepts, this layout has reduced gate to source/drain overlap capacitances which is necessary for high speed applications. The use of SEG instead of blanket epitaxy avoids the deterioration of the Si–SiO 2 interface due to reactive ion etching (RIE) and reduces punch-through due to facet growth. First non-optimized p-channel MOSFETs with a 12-nm gate oxide show a transconductance of 90 mS/mm. The cut-off frequencies of this device turned out to be f T =2.3 GHz and f max =1.1 GHz.

Patterning of 25-nm-wide silicon webs with an aspect ratio of 13

Some of the main problems associated with downscaling of devices are short channel effects and lithography limitations. The double gate concept is known to improve short channel behaviour of MOSFETs. One vertical double gate MOSFET concept requires for the active region silicon webs 300 nm in height and less than 20 nm in width. Subsequent processing means the webs should originally be 10 nm wider than this. Electron beam lithography and reactive ion etching were used to obtain these 25-30-nm-wide silicon webs. To define the structures, hydrogen silsesquioxane (HSQ) was used as electron beam resist; 23-nm-wide and 110-nm-high lines in HSQ were obtained. These structures were tranferred by dry etching with a HBr/O2 plasma and an inductive coupled plasma (ICP) source. This resulted in 25-nm-wide and 330-nm-high silicon webs.

Single cell recordings with pairs of complementary transistors

Floating gate field-effect transistors (FETs) for the detection of extracellular signals from electrogenic cells were fabricated in a complementary metal oxide semiconductor process. Additional passivation layers protected the transistor gates from the electrolyte solution. To compare the signals from n- and p-FETs, two electronically separated, but locally adjacent transistors were combined to one measuring unit. The paired sensing area of this unit had the dimension of a single cell. Simultaneous recordings with n- and p-channel floating gate FETs from a single cell exhibited comparable amplitudes and identical time courses. The experiments indicate that both types of FETs express similar sensitivities.

Vertical p-MOSFETs with gate oxide deposition before selective epitaxial growth

Abstract A novel vertical MOSFET concept using selective epitaxial growth by low pressure chemical vapor deposition is proposed and the first p-channel device characteristics measured are described. In contrast to other MOS technologies, the gate oxide is deposited before epitaxy, and therefore it exists before the channel region is grown. Compared to planar layouts, the vertical layout increases the packing density without the use of advanced lithography; the extent of the increase depends on application. Compared to other vertical transistors, this concept reduces overlap capacitance and offers the possibility of three-dimensional integration. Vertical p-channel MOSFETs with a channel length LG down to 130 nm and a gate oxide thickness dox down to 12 nm have been fabricated and yield a transconductance of 100 mS mm−1.

Top contacts for vertical double-gate MOSFETs

As scaling of electronic devices goes on, the issue of short channel effects draws growing attention. Double-gate MOSFETs are known to reduce short channel behaviour effectively [Proc. IEEE 85 (1997) 486] and therefore have gained increasing attention for future CMOS application. Here a vertical layout is discussed, where the current flow is perpendicular to the surface. In an already realised layout [Proc. ESSDERC (2001) 191] the device performance is ruled by the resistance of the top contact. In a revised layout the top contact is implemented directly on top of the transistor. Here the layout and the technology steps to obtain this structure are discussed.

Vertical p-channel double-gate MOSFETs

Double-gate MOSFETs have drawn increasing interest within the last years because of their capability to reduce short channel effects. In this work a p-channel double-gate MOSFET layout was realised. Based on epitaxial growth and subsequent ion implantation, the p/n/p-doping profile is implemented in vertical sequence. P-channel devices with channel lengths of 50 nm and gate oxide thickness of 6.6 nm show transconductances of 480 /spl mu/S//spl mu/m, subthreshold slope of 126 mV/dec and DIBL of 80 mV/V.

Vertical Double-Gate MOSFET based on epitaxial growth by LPCVD

A vertical MOSFET layout aiming a double gate structure is proposed. DoubleGate MOSFETs are known to reduce short channel behaviour effectively [1] and are a promising candidate for sub 50nm MOSFET design. The vertical layout discussed here is based on epitaxial growth by LPCVD. From in situ doped samples pchannel MOSFETs with a channel length Lg of 100nm and gate oxide thickness dox of 6nm were fabricated. These first transistors show transconductances of up to 41μS/μm.

The disposable dot FET: A strained silicon channel on top of removed SiGe

This paper presents a silicon MOSFET device, which utilizes locally strained silicon layers for high mobility channels. By means of template-assisted self assembly of Ge-islands and Silicon overgrowth a Silicon layer is formed, which is strained on top of the very accurately placed Ge-islands and their near vicinity. The island formation in the seed holes on pre patterned substrates and the intrinsic overlay of the ebeam lithography were investigated. The island size, shape and distribution can be properly controlled up to a grid pitch of 700 nm. The intrinsic overlay of ±10nm can be maintained during device processing, which is due to the symmetry of the markers.