St. Trellenkamp

Patterning of 25-nm-wide silicon webs with an aspect ratio of 13

Some of the main problems associated with downscaling of devices are short channel effects and lithography limitations. The double gate concept is known to improve short channel behaviour of MOSFETs. One vertical double gate MOSFET concept requires for the active region silicon webs 300 nm in height and less than 20 nm in width. Subsequent processing means the webs should originally be 10 nm wider than this. Electron beam lithography and reactive ion etching were used to obtain these 25-30-nm-wide silicon webs. To define the structures, hydrogen silsesquioxane (HSQ) was used as electron beam resist; 23-nm-wide and 110-nm-high lines in HSQ were obtained. These structures were tranferred by dry etching with a HBr/O2 plasma and an inductive coupled plasma (ICP) source. This resulted in 25-nm-wide and 330-nm-high silicon webs.

Top contacts for vertical double-gate MOSFETs

As scaling of electronic devices goes on, the issue of short channel effects draws growing attention. Double-gate MOSFETs are known to reduce short channel behaviour effectively [Proc. IEEE 85 (1997) 486] and therefore have gained increasing attention for future CMOS application. Here a vertical layout is discussed, where the current flow is perpendicular to the surface. In an already realised layout [Proc. ESSDERC (2001) 191] the device performance is ruled by the resistance of the top contact. In a revised layout the top contact is implemented directly on top of the transistor. Here the layout and the technology steps to obtain this structure are discussed.

Phenomenological considerations of resistively switching TiO 2 in nano crossbar arrays

Within this paper we present the fabrication of nano crosspoint junctions and arrays with electron beam direct writing (EBDW). Reactively sputtered TiO2 was incorporated as a resistively switching thin film and electrically characterized concerning its performance. These devices are suitable for novel non-volatile storage systems in form of resistive random access memories (RRAM). All used materials as well as the fabrication processes for the functional thin film are in good accordance with current and future CMOS technology and provide a way to achieve low cost, high density non-volatile memory. The experiments were performed with 100 ⋅ 100 nm2 small single junctions and arrays with 200 nm wide wires. The results of the former prove a non-volatility for more than 105 s and a switching speed better than 10 ns for the SET- and RESET operation (from high to low resistance state and in reverse direction). The latter prove the direct addressability of junctions within an array.

Vertical p-channel double-gate MOSFETs

Double-gate MOSFETs have drawn increasing interest within the last years because of their capability to reduce short channel effects. In this work a p-channel double-gate MOSFET layout was realised. Based on epitaxial growth and subsequent ion implantation, the p/n/p-doping profile is implemented in vertical sequence. P-channel devices with channel lengths of 50 nm and gate oxide thickness of 6.6 nm show transconductances of 480 /spl mu/S//spl mu/m, subthreshold slope of 126 mV/dec and DIBL of 80 mV/V.

The disposable dot FET: A strained silicon channel on top of removed SiGe

This paper presents a silicon MOSFET device, which utilizes locally strained silicon layers for high mobility channels. By means of template-assisted self assembly of Ge-islands and Silicon overgrowth a Silicon layer is formed, which is strained on top of the very accurately placed Ge-islands and their near vicinity. The island formation in the seed holes on pre patterned substrates and the intrinsic overlay of the ebeam lithography were investigated. The island size, shape and distribution can be properly controlled up to a grid pitch of 700 nm. The intrinsic overlay of ±10nm can be maintained during device processing, which is due to the symmetry of the markers.

Vertical double-gate MOSFETs

The downscaling of MOSFET devices will proceed at least for the next 15 years. It is questionable, if the normal, lateral MOSFET can be scaled below 50 nm channel length, which will be reached soon. In this range, the short channel effects, which have been suppressed by improving the lateral bulk MOSFET, demand new device architectures to improve electrical performance. Therefore new layouts as ultra thin body devices and multiple gate MOSFET are developed within the last years. In this work we present a vertical double-gate MOSFET layout, where the current flow is perpendicular to the suiface. For the realization of this layout no SOl-substrate and only one sub-50 nm lithography are needed, resulting in an easier and hence cheaper process flow compared to other multigate layouts. P- and n-channel devices show a transconductance of 150p.SIp.m and 195 μSμm, respectively, and a subthresholdslope S of80 mVidec.

Fabrication of UV sources for novel lithographical techniques: Development of nano-LED etching procedures

The development of two different dry etching approaches - ion beam etching (IBE) and reactive ion etching (RIE) - is reported for the fabrication of nano-LEDs as UV sources. The IBE approach leads to nano-LEDs with higher emission intensity but with rougher side-walls and broader FWHM.

InGaN mesoscopic structures for low energy consumption nano-opto-electronics

Nano-LEDs based on mesoscopic structures are the key elements for future energy saving nano-opto-electronics as well as for fast and highly secure optical communication. We present first results using a vertical device layout in which nano-LED emitters based on InGaN mesoscopic structures deposited by metalorganic vapor phase epitaxy (MOVPE) were implemented. The nano-LEDs were integrated in a vertical device layout without degradation of their optical and electrical properties. The results presented demonstrate the great promise of the novel device concept and integration technology for low energy consumption nano-opto-electronics operated in the telecommunication wavelength range.

Templates for highly ordered SiGe-QD arrays for single photon detection

Two and three dimensional SiGe-QD-arrays can be regarded as a test-system for artificial crystals, as they also can be utilized as single photon detectors. While arrays with randomly distributed SiGe-QD can easily be grown on plain silicon surfaces, the fabrication of ordered arrays with pitches done to a few 10 nm is challenging: to facilitate Template Assisted Self Assembled growth of SiGe-QD in MBE, ordered arrays of seed holes have to be etched into the silicon substrate. EUV-interference lithography can be employed, but here no spatial relation to previous or later process steps is possible. In this work contrast and resolution of ZEP 520A-7 is investigated in terms of development temperature, duration and acceleration voltage during e-beam exposure to obtain laterally ordered well localized SiGe-QD-arrays. By increasing acceleration voltage from 50 kV to 100 kV contrast can be improved by a factor of 1.9, shifting the resolution from 40 nm pitch seed hole arrays etched in silicon to 30 nm.

The disposable Dot Field Effect Transistor: Process flow and overlay requirements

The progress in the field of MOSFET devices was facilitated by the downscaling of their dimensions. To maintain device performance, the lateral layout was improved continually, but in recent years new device architectures as Ultra Thin Body and Multi Gate devices were discussed. Furthermore new materials were introduced as high-K gate dielectrics and metal gates. Today the advantages of strained silicon as material for the channel are investigated. The strained material offers the advantage of a higher carrier mobility, which leads to a better Ion/Ioff-ratio. In this work a device process using locally strained silicon by means of template-assisted self-assembly is proposed.