J. Raja Paul Perinbam

FPGA Implementation of Integer Transform and Quantizer for H.264 Encoder

This paper deals with the process of Transformation and Quantization that is carried out on each inter-predicted residual block in a video encoding process and their reduced complexity hardware implementation. H.264/AVC utilizes 4 × 4 integer transform, which is derived from the 4 × 4 DCT. We propose, a reduced complexity algorithm and a pipelined structure for the Core forward integer transform module. A multiplier-less architecture is realized with less number of shifts and adds compared to existing works. The corresponding inverse transform is exactly reversible. Each of the transformed coefficients is quantized by a scalar quantizer. The quantization step size can be varied from macroblock to macroblock. The proposed unified pipelined architecture outperforms many recent implementations in terms of gate count and is capable of processing a 4 × 4 residual block in 4 clock cycles.

A Novel Low Power 16X16 Content Addressable Memory Using PA

This paper presents a novel low power content addressable memory (CAM) using pass transistor adiabatic logic (PAL). The PAL CAM uses adiabatic principle in the read, write and compare operations. The SPICE simulation of 16/spl times/16 CAM indicates around 95% of power saving at 10MHz operating frequency compared to conventional design. The circuits are designed using 0.6/spl mu/m CMOS technology.

A low-jitter phase-locked loop architecture for clock generation in Analog to Digital Converters

This paper presents the circuit level implementation and analysis of the Phase Locked Loop (PLL) architecture for clock generation in Analog to Digital Converters (ADCs). The PLLs are required to generate low-noise or low-jitter clock signals and at the same time need to achieve fast locking. The Analog to Digital Converters require a clock generator whose clock output should have jitter less than 1 ps to have higher Effective Number Of Bits (ENOB). Catering the needs of the ADC, low-jitter PLL architecture is proposed which consist of pre-charged phase-frequency detector, charge pump, second order loop filter and a current-starved inverter based Voltage Controlled Oscillator (VCO) circuit. The integrated PLL architecture is implemented and simulated using CADENCE Analog Design Environment. It is synthesized using TSMC 0.18µm, six-metal technology. The lock range (operating frequency range) of the PLL is 95MHz to 145 MHz with a center frequency of 100 MHz and a jitter of around 700 fs are obtained as a result of its verification at all process corners.

Low jitter all digital phase locked loop based clock generator for high speed system on-chip applications

An efficient architecture for a low jitter all digital phase locked loop (ADPLL) suitable for high speed system-on-chip (SoC) applications is presented in this article. The ADPLL is designed using standard cells and described by hardware description language. The ADPLL implemented in a 90-nm CMOS process can operate from 10 to 200 MHz and achieve worst case frequency acquisition in 14 reference clock cycles. The simulation result shows that the PLL has a cycle to cycle jitter of 164 ps at 100 MHz. Because the digitally controlled oscillator can achieve both high resolution and wide frequency range, it can meet the demands of system-level integration. The proposed ADPLL can easily be ported to different processes in a short time. Thus, it can reduce the design time and design complexity of the ADPLL, making it very suitable for SoC applications.

A novel 14 ∼ 170 MHz All digital delay locked loop with ultra fast locking for SoC applications

A delay locked loop (DLL) is a feedback control system that equalizes the phase of two delayed copies of the same clock signal. The DLL is useful for compensating the clock distribution delays that arise in many system configurations. An all-digital delay-locked loop (ADDLL) is presented to achieve wide range of operation, fast lock, Harmonic-Free and process immunity. The paper proposes a Modified Variable Successive Approximation Register-controlled (MVSAR) algorithm to achieve the fast-locking property, closed-loop operation and performing binary search without harmonic-locking issue. The fast locking of proposed MVSAR is verified by comparing it with the existing architectures. The proposed ADDLL is implemented at system level with standard cells and it has good portability over different processes. It is synthesized using TSMC 0.18µm, six-metal technology. The lock range (operating frequency range) of the ADDLL is 14MHz to 170 MHz and occupied an area (physical design) of 142*142 Sq.µm (0.020164 Sq.mm).

High speed, low power 100 MS/s front end track-and-hold amplifier for ten-bit pipelined ADC

The work focuses on the design of a high speed, low power track-and-hold amplifier (THA) for ten-bit 100 MS/s pipelined analogue-to-digital converter (ADC). A wide bandwidth and high gain two-stage operational transconductance amplifier (OTA) is selected as OTA of THA. This OTA consumes less amount of power and produce less thermal noise. The bootstrap technique is employed to reduce the non-linearity error associated with the input signal. The signal swing of the circuit is allowed to exceed the supply voltage (1.8 V), which further reduces the thermal noise contributed by the circuit and increases the dynamic range (DR) of the circuit. The circuit is implemented in UMC 180 nm digital CMOS technology. The THA circuit along with the biasing circuit consumes 5.706 mW power and it achieves 81.23 dB as the spurious free dynamic range (SFDR) for 2 V output at 100 MHz sampling rate. The dynamic range of the THA is 85.94 dB. The proposed THA is simulated using SPECTRE simulator under a variety of process and temperature conditions.

Fully pipelined parallel architecture for candidate block and pixel-subsampling-based motion estimation

This paper presents a low power and high speed architecture for motion estimation with Candidate Block and Pixel Subsampling (CBPS) Algorithm. Coarse-to-fine search approach is employed to find the motion vector so that the local minima problem is totally eliminated. Pixel subsampling is performed in the selected candidate blocks which significantly reduces computational cost with low quality degradation. The architecture developed is a fully pipelined parallel design with 9 processing elements. Two different methods are deployed to reduce the power consumption, parallel and pipelined implementation and parallel accessing to memory. For processing 30 CIF frames per second our architecture requires a clock frequency of 4.5 MHz.

A 52.6 mW 10-bit, 100 MS/s Pipelined CMOS Analog-To-Digital Converter

The design of 10-bit, 100 MS/s, pipelined analog-to-digital converter (ADC) is presented. A wide-bandwidth and high gain two-stage operational trans-conductance amplifier (OTA) is used in Track-and-Hold Amplifier (THA) and Multiplying Digital-to-Analog Converter (MDAC) sections, to reduce power consumption and thermal noise contribution by the ADC. The signal swing of the analog functional blocks (THA and MDAC sections) is allowed to exceed the supply voltage (1.8 V), which further reduces the thermal noise contributed by the circuit and increases the dynamic range of the circuit. Charge sharing comparator is proposed in this work, which reduces the dynamic power dissipation and kick-back noise of the comparator circuit. The bootstrap technique and bottom plate sampling technique is employed in THA and MDAC sections to reduce the non-linearity error associated with the input signal resulting in a signal to noise distortion ratio of 58.72 dB/57.57 dB @ 2 MHz/ Nyquist frequency respectively. The maximum differential non-linearity (DNL) is +0.6167/ -0.3151 LSB and the maximum integral nonlinearity (INL) is +0.4271/-0.4712 LSB. The dynamic range of the ADC is 58.72 dB for full scale input signal @ 2 MHz input frequency. The ADC consumes 52.6 mW at 100 MS/s sampling rate. The circuit is implemented using UMC-180 nm digital CMOS technology.