S. Moorthi

Implementation of hybrid ANN-PSO algorithm on FPGA for harmonic estimation

Harmonic estimation is the main process in active filters for harmonic reduction. A hybrid Adaptive Neural Network-Particle Swarm Optimization (ANN-PSO) algorithm is being proposed for harmonic isolation. Originally Fourier Transformation is used to analyze a distorted wave. In order to improve the convergence rate and processing speed an Adaptive Neural Network Algorithm called Adaline has then been used. A further improvement has been provided to reduce the error and increase the fineness of harmonic isolation by combining PSO algorithm with Adaline algorithm. The inertia weight factor of PSO is combined along with the weight factor of Adaline and trained in Neural Network environment for better results. ANN-PSO provides uniform convergence with the convergence rate comparable that of Adaline algorithm. The proposed ANN-PSO algorithm is implemented on an FPGA. To validate the performance of ANN-PSO; results are compared with Adaline algorithm and presented herein.

NoC Based Distributed Partitionable Memory System for a Coarse Grain Reconfigurable Architecture

This paper presents a Network-on-Chip based distributed partitionable memory system for a Dynamic Reconfigurable Resource Array (DRRA). The main purpose of this design is to extend the Register File (RFile) interface with additional data handling capability. The proposed interconnect which enables the interaction between existing partition of computation fabric and the distributed memory system is programmable and partitionable. The system can modify its memory to computation element ratio at runtime. The interconnect can provide multiple interfaces that can support upto 8 GB/s per interface.

Embedded Control of n -Level DC–DC–AC Inverter

A generalized multilevel inverter (MLI) with frontend dc-dc conversion stage followed by a synchronized H-bridge is presented. By using this configuration along with the proposed embedded control, any desired number of levels (n) in the output voltage can be produced. The dc-dc conversion stage employs an asynchronous buck converter. The duty cycle of dc-dc converter is varied in the form of m-level piecewise constant (PWC) unidirectional sine wave to produce a similar output voltage across the dc-link capacitor. The unidirectional PWC voltage is made into n-level ac voltage, where n = (2m - 1), by the synchronized H-bridge. Hence, it is named as dc-dc-ac MLI. An 8-bit Xilinx SPARTAN 3AN field programmable gate array (FPGA)-based digital controller is utilized for the simultaneous generation of high-frequency switching pulses for dc-dc converter and synchronized fundamental frequency switching pulses for H-bridge. The desired number of levels in ac output voltage and its frequency are the essential inputs to the pulse generation algorithm implemented in FPGA. The proposed MLI is simulated in MATLAB/Simulink environment; its functioning is verified with resistive (R) and resistive-inductive (R-L) loads. The hardware prototype of MLI is built in the laboratory and its performance is validated with R, R-L loads, and few home appliances.

A systematic design approach for low-power 10-bit 100MS/s pipelined ADC

A systematic design approach for low-power 10-bit, 100MS/s pipelined analog-to-digital converter (ADC) is presented. At architectural level various per-stage-resolution are analyzed and most suitable architecture is selected for designing 10-bit, 100MS/s pipeline ADC. At Circuit level a modified wide-bandwidth and high-gain two-stage operational transconductance amplifier (OTA) proposed in this work is used in track-and-hold amplifier (THA) and multiplying digital-to-analog converter (MDAC) sections, to reduce power consumption and thermal noise contribution by the ADC. The signal swing of the analog functional blocks (THA and MDAC sections) is allowed to exceed the supply voltage (1.8V), which further increases the dynamic range of the circuit. Charge-sharing comparator is proposed in this work, which reduces the dynamic power dissipation and kickback noise of the comparator circuit. The bootstrap technique and bottom plate sampling technique is employed in THA and MDAC sections to reduce the nonlinearity error associated with the input signal resulting in a signal-to-noise-distortion ratio of 58.72/57.57dB at 2MHz/Nyquist frequency, respectively. The maximum differential nonlinearity (DNL) is +0.6167/-0.3151LSB and the maximum integral nonlinearity (INL) is +0.4271/-0.4712LSB. The dynamic range of the ADC is 58.72dB for full-scale input signal at 2MHz input frequency. The ADC consumes 52.6mW at 100MS/s sampling rate. The circuit is implemented using UMC-180nm digital CMOS technology.

Design, Operation, and Control of S3 Inverter for Single-Phase Microgrid Applications

A single-phase voltage source inverter with a front-end dc-dc conversion stage followed by a synchronized push-pull configuration operating at a desired fundamental frequency (FF) is presented. The duty cycle of the dc-dc conversion stage is varied in the form of a unidirectional sine wave to produce a similar output voltage across the dc-link capacitor. The unidirectional voltage is made into an alternating voltage by the synchronized push-pull configuration. This inverter employs three semiconductor switches, in which one is operating at a high frequency and the rest are operating at an FF. Hence, it is named as the S3 inverter. Furthermore, simple and cost-effective analog circuits are presented for the generation of switching pulses and the control of the amount of power fed to the grid. The hardware prototype of the S3 inverter has been built in a laboratory, and its performance during the stand-alone and grid-connected modes of operation is validated.

FPGA Based Implementation of Variable-Voltage Variable-Frequency Controller for a Three Phase Induction Motor

This paper presents the design and implementation of a Variable-Voltage Variable-Frequency (VVVF) Controller based on Sinusoidal Pulse Width Modulation (SPWM) Technique for a 3 Phase Induction Motor using a Field Programmable Gate Array (FPGA). The work involves implementation of an Open loop control scheme for an induction motor. The technique is used extensively in the industry as it provides the accuracy required at minimal cost. Voltage/ frequency (v/f) controlled motors fall under the category of Variable Voltage Variable Frequency (VVVF) drives. To maintain maximum torque for a given working condition, the flux in the machine must be maintained constant. In other words, the ratio of Voltage to frequency must be held constant. For Variable Voltage Variable Frequency (VVVF) drives, there is a need to control the fundamental voltage of the inverter if its frequency (and therefore the frequency of the induction motor), need to be varied. To vary the fundamental component of the inverter, the Modulation Index of the carrier signal has to be changed. The speed at rated supply frequency is normally used as the base speed. At frequencies below the base speed, the supply magnitude needs to be reduced so as to maintain a constant Volt/Hertz. The FPGA controller is used to generate SPWM pulses based on the frequency input, that are used to control the inverter. The VVVF output of the inverter can be used as supply to a three phase induction motor and thereby speed of the motor can be controlled.

A NoC based distributed memory architecture with programmable and partitionable capabilities

The paper focuses on the design of a Network-on-chip based programmable and partitionable distributed memory architecture which can be integrated with a Coarse Grain Reconfigurable Architecture (CGRA). The proposed interconnect enables better interaction between computation fabric and memory fabric. The system can modify its memory to computation element ratio at runtime. The extensive capabilities of the memory system are analyzed by interfacing it with a Dynamically Reconfigurable Resource Array (DRRA), a CGRA. The interconnect can provide multiple interfaces which supports upto 8 GB/s per interface.

Harmonic estimation using Modified ADALINE algorithm with Time-Variant Widrow — Hoff (TVWH) learning rule

Algorithms are well developed for adaptive estimation of selected harmonic components in Digital Signal Processing. In power electronic applications, objectives like fast response of a system is of primary importance. An effective active power filtering for estimation of instantaneous harmonic components is presented in this paper. A signal processing technique using Modified Adaptive Neural Network (Modified ANN) algorithm has been proposed for harmonic estimation. Its primary function is to estimate harmonic components from selected signal (Current or Voltage) and it requires only the knowledge of the frequency of the component to be estimated. This method can be applied to a wide range of equipments. The validity of the proposed method to estimate voltage harmonics is proved with a dc/ac inverter as an example and the simulation results are compared with ADALINE algorithm for illustrating its effectiveness.

Ethernet based industry automation using FPGA

The aim of this work is to develop an embedded system directed at automating appliances in an industry via Ethernet. The system employs server/client architecture; switching commands for the appliances which are connected to the client can be received and displayed at either end. The data containing information about the control commands are transferred between the end points of communication using Transmission Control Protocol (TCP). The remote host processes the commands received and translates them into actions of switching particular appliances ON or OFF. This type of control system gives the liberty for control of appliances from remote locations connected through Ethernet. A novel embedded system has been designed, implemented on Field Programmable Gate Arrays (FPGAs) and a small-scale prototype is developed and tested.

Modified ADALINE algorithm for harmonic estimation and selective harmonic elimination in inverters

In digital signal processing, algorithms are very well developed for the estimation of harmonic components. In power electronic applications, an objective like fast response of a system is of primary importance. An effective method for the estimation of instantaneous harmonic components, along with conventional harmonic elimination technique, is presented in this article. The primary function is to eliminate undesirable higher harmonic components from the selected signal (current or voltage) and it requires only the knowledge of the frequency of the component to be eliminated. A signal processing technique using modified ADALINE algorithm has been proposed for harmonic estimation. The proposed method stays effective as it converges to a minimum error and brings out a finer estimation. A conventional control based on pulse width modulation for selective harmonic elimination is used to eliminate harmonic components after its estimation. This method can be applied to a wide range of equipment. The validity of the proposed method to estimate and eliminate voltage harmonics is proved with a dc/ac inverter as a simulation example. Then, the results are compared with existing ADALINE algorithm for illustrating its effectiveness.