J. Robert Heath

Classification Categories and Historical Development of Circuit Switching Topologies

A broad tutorial survey is given of the various topologies available for use in circuit switching systems for tightly coupled parallel/distributed computer systems. Terminology and issues of circuit switching as related to parallel/distributed processing are first discussed. Circuit switching networks are then classified according to connection capability, topological geometry, and basis of development. Topological relationships of specific networks are addressed. 91 references.

A New Multichannel, Coherent Amplitude Modulated, Time-Division Multiplexed, Software-Defined Radio Receiver Architecture, and Field-Programmable-Gate-Array Technology Implementation

Some wireless communication systems must be able to receive and process signals from multiple source stations simultaneously. A common practice is to use multiple duplicated hardware resources; a different set of resources for each received station. A new coherent amplitude modulated (AM), time-division multiplexed (TDM), receiver system architecture and design, based on the software-defined radio (SDR) standard, is proposed, developed and validated via simulation and experimental hardware prototype testing. The new receiver system architecture and approach enables reception and processing of signals from multiple stations using the hardware resources normally needed for reception and processing of only one station. Production models of the proposed receiver/processing system architecture and design would be implemented in programmable-logic-device (PLD) technology [field-programmable-gate-array (FPGA) in our case] to accommodate rapidly changing communication protocols and standards and to enhance processing performance.

How to Write a Universal Cross-Assembler

Most microprocessors require their own cross-assemblers-an expensive proposition for organizations with a variety of micros. Whats the answer? A universal one-pass cross-assembler.

A Handheld Programmable-Logic-Device-Based Temperature and Relative-Humidity Sensor, Processor, and Display System Platform for Automation and Control of Industry Processes

The development, testing, and validation of a small versatile battery-powered handheld programmable-logic-device (PLD)-based temperature and relative-humidity (RH) sensor, processor, and display system platform is addressed in this paper. An initial and illustrative application of the platform, which is used for its validation-temperature and RH sensing, calculation, and display of equilibrium moisture content of wood, is described. The platform may be utilized for computation and display of a range of temperature- and RH-sensitive metrics/parameters of importance to other process industries. The cost of the platform is important but not the highest priority. As illustrated in the wood-process-industry application of the platform, a higher priority is an ability to efficiently explore, implement, and compare, in a timely manner, different processor microarchitectures and display system formats which may be used in the calculation and display of any process-industry temperature- and/or RH-dependent process metric(s). This could include simultaneous calculation and display of multiple metrics which are a function of temperature and RH. After comparison, a best processor microarchitecture and display system can then be chosen and implemented based on specific industry process application performance/cost and other requirements. A PLD-based sensor, processor, and display system platform offers this opportunity.

A multi-channel coherent Amplitude Modulated Time Division Multiplexed Software Defined Radio receiver architecture for Programmable-Logic-Device technology implementation

Some wireless communication systems must be able to receive and process signals from multiple source channels (stations) simultaneously. A common practice is to use multiple duplicated hardware resources; a different set of resources for each received channel. A new coherent Amplitude Modulated (AM) Time Division Multiplexed (TDM) receiver system architecture and design, based on the Software Defined Radio (SDR) standard, is proposed, developed and validated via simulation and experimental hardware prototype testing. The new receiver system architecture and approach enables reception and processing of signals from multiple channels using the hardware resources normally needed for reception and processing of only one channel. Production models of the proposed receiver/processing system architecture and design would be implemented to Programmable-Logic-Device (PLD) technology to accommodate rapidly changing communication protocols and standards and to enhance processing performance.

FPGA based parallel architecture implementation of Stacked Error Diffusion algorithm

Digital halftoning is a crucial technique used in digital printers to convert a continuous-tone image into a pattern of black and white dots. Halftoning is used since printers have a limited availability of inks and cannot reproduce all the color intensities in a continuous image. Error Diffusion is an algorithm in halftoning that iteratively quantizes pixels in a neighborhood dependent fashion. This manuscript focuses on the development, design and Hardware Description Language (HDL) functional and performance simulation validation of a parallel scalable hardware architecture for high performance implementation of a high quality Stacked Error Diffusion algorithm. A CMYK printer, utilizing the high quality error diffusion algorithm, would be required to execute error diffusion 16 times per pixel, resulting in a potentially high computational cost. The algorithm, originally described in ‘C’, requires a significant processing time when implemented on a conventional single Central Processing Unit (CPU) based computer system. Thus, a new scalable high performance parallel hardware processor architecture is developed to implement the algorithm and is implemented to and tested on a single Programmable Logic Device (PLD) based Field Programmable Gate Array (FPGA) chip. There is a significant decrease in the run time of the algorithm when run on the newly proposed parallel architecture implemented to FPGA technology compared to execution on a single CPU based system.

New systolic array processor architecture for simultaneous discrete convolution of an image plane with multiple filter coefficient sets

A new high-performance scalable systolic array processor architecture module for implementation of the two-dimensional discrete convolution algorithm on an (i×j) pixel input image plane (IP) using an (n×n) filter coefficient (FC) plane is first presented. The module generates one convoluted output image (OI) plane pixel per system clock cycle for an (n×n) FC plane using a level of r hardware resources. Second, the architecture is extended in a modular scalable manner to allow simultaneous convolution of a single IP, with k different (n×n) FC planes, such that k convoluted OI plane pixels are generated each system clock cycle, utilizing less than (k*r) hardware resources. The new convolution architecture may be implemented to an ASIC or programmable logic device (PLD) platform. Results of synthesizing and implementing the proposed architecture are shown, illustrating the scalability of the new convolution architecture relative to k. Results from postimplementation virtual hardware prototype simulation testing and from testing a PLD-based experimental hardware prototype are shown that validate correct functional and performance operation of the new convolution architecture module.