Michael E. Lhamon

A multi-channel coherent Amplitude Modulated Time Division Multiplexed Software Defined Radio receiver architecture for Programmable-Logic-Device technology implementation

Some wireless communication systems must be able to receive and process signals from multiple source channels (stations) simultaneously. A common practice is to use multiple duplicated hardware resources; a different set of resources for each received channel. A new coherent Amplitude Modulated (AM) Time Division Multiplexed (TDM) receiver system architecture and design, based on the Software Defined Radio (SDR) standard, is proposed, developed and validated via simulation and experimental hardware prototype testing. The new receiver system architecture and approach enables reception and processing of signals from multiple channels using the hardware resources normally needed for reception and processing of only one channel. Production models of the proposed receiver/processing system architecture and design would be implemented to Programmable-Logic-Device (PLD) technology to accommodate rapidly changing communication protocols and standards and to enhance processing performance.

Converting color values using stochastic interpolation

This paper presents a method of efficiently converting from a set of noisy color values to a set of device colorants. Using a deterministic process, 24-bit scanned color values are reduced to dithered 12-bit RGB table indices. After the reduction, a small but complete lookup table with 4096 entries converts the RGB values directly to the output color space. This stochastic interpolation process, while minimizing banding and abrupt color transitions, eliminates the need for trilinear interpolation of the data and significantly reduces the size of the lookup table.

New systolic array processor architecture for simultaneous discrete convolution of an image plane with multiple filter coefficient sets

A new high-performance scalable systolic array processor architecture module for implementation of the two-dimensional discrete convolution algorithm on an (i×j) pixel input image plane (IP) using an (n×n) filter coefficient (FC) plane is first presented. The module generates one convoluted output image (OI) plane pixel per system clock cycle for an (n×n) FC plane using a level of r hardware resources. Second, the architecture is extended in a modular scalable manner to allow simultaneous convolution of a single IP, with k different (n×n) FC planes, such that k convoluted OI plane pixels are generated each system clock cycle, utilizing less than (k*r) hardware resources. The new convolution architecture may be implemented to an ASIC or programmable logic device (PLD) platform. Results of synthesizing and implementing the proposed architecture are shown, illustrating the scalability of the new convolution architecture relative to k. Results from postimplementation virtual hardware prototype simulation testing and from testing a PLD-based experimental hardware prototype are shown that validate correct functional and performance operation of the new convolution architecture module.