J.S. Hamel

Two-dimensional analysis of emitter resistance in the presence of interfacial oxide breakup in polysilicon emitter bipolar transistors

Two-dimensional computer simulations of the emitter resistance and majority carrier current flow in the presence of interfacial oxide breakup in polysilicon emitter bipolar transistors are shown and compared with published experimental results. The analysis reveals that the behavior of the emitter resistance with oxide layer breakup can be adequately predicted only if 2-D majority carrier current flow is taken into account. The interfacial layer plays an important role in determining the emitter resistivity only in very early stages of oxide layer breakup. Both the experimental data and the analysis reveal a much faster fall-off in emitter resistance with oxide layer breakup than previous 1-D dimensional theoretical analyses have suggested. The 2-D majority carrier modeling presented suggests that the emitter resistance decreases much more rapidly than the current gain in the early stages of oxide layer breakup. Physical mechanisms which explain the differences in the dependence of the emitter resistance and gain on oxide layer breakup are proposed. >

Technological requirements for a lateral SiGe HBT technology including theoretical performance predictions relative to vertical SiGe HBTs

A new class of bipolar transistors, lateral SiGe HBTs, is considered from a theoretical point of view with regard to their feasibility and potential radio frequency (RF)/microwave performance relative to existing vertical SiGe HBT technologies. Using numerical analysis, it is found that the low terminal parasitics of a lateral SiGe HBT structure can provide at least twice the unity power gain frequency f/sub max/ compared to vertical structures for a given minimum lithography. Methods to fabricate a lateral SiGe HBT with superior RF/microwave characteristics compared to existing vertical technologies are explored. Extension of the numerical analysis results using simple scaling rules reveals that it should be possible to fabricate lateral SiGe HBTs with unity power gain frequencies in the neighborhood of 500 GHz operating in the micro-ampere range.

An accurate quasi-static method for determining the excess phase shift in the base region of bipolar transistors

The conventional quasi-static approach has been extended to enable the accurate calculation of the phase shift of the common emitter current gain up to the transition frequency solely from static charge distributions for bipolar transistors with arbitrary base impurity profiles. Accurate knowledge of the phase shift allows the use of simple, yet accurate, high-frequency compact bipolar transistor models which use this information to determine critical model parameters. The accuracy of this approach was assessed by AC numerical simulation. The ability of the approach to estimate the phase shift of the common emitter current gain from static charge distributions allows accurate predictive high-frequency AC modeling of both digital and analog bipolar and BiCMOS circuits without the need for high-frequency, time-dependent device simulation or high-frequency device measurements.<<ETX>>

Trade-off between emitter resistance and current gain in polysilicon emitter bipolar transistors with intentionally grown interfacial oxide layers

Experimental measurements of emitter resistance and current gain in polysilicon emitter bipolar transistors that have received annealing to break up an intentionally grown RCA oxide interfacial layer are presented. An anneal of 900 degrees C for 10 min in a nitrogen ambient of the interfacial layer prior to polysilicon doping resulted in a decrease in emitter resistance by approximately a factor of 5, with an increase in base saturation current of only 25% while still maintaining a current gain of around 500. The authors believe that this is the largest trade-off in emitter resistance versus current gain demonstrated so far for polysilicon transistors with an RCA interfacial layer. These results support a theory previously proposed by the authors (1991) predicting that significant trade-offs between emitter resistance and current gain can be obtained if an intentionally grown interfacial oxide layer in polysilicon emitter bipolar transistors is annealed so as to induce only partial breakup such that most of the layer remains intact.<<ETX>>

Integral relations for determining non-quasi-static charge partitioning in bipolar devices from static charge distributions

Integral relations are rigorously derived for the non-quasi-static charge partitioning in bipolar devices in terms of static carrier distributions in low-level injection. The resulting expressions are simpler than previous charge partitioning expressions for arbitrary impurity profiles and, in contrast to previous expressions, take into account minority-carrier recombination, which is required in the emitter region of bipolar transistors. The simplicity of the derived integral relations permits the development of a semianalytic expression for the charge partitioning in the base region which does not require a static minority carrier solution, and which is similar in computational complexity to the base transit line. >

A simple expression for ECL propagation delay including non-quasi-static effects

Abstract A simple, analytical, expression for the emitter-coupled logic (ECL) propagation delay is useful not only in predicting the performance of ECL circuits, but as a figure of merit for use in the design and “optimisation” of bipolar transistors used in nonsaturating logic applications. A simple expression for the propagation delay time of a differential pair with an ideal, non-inverting output buffer is obtained from an analysis, in the s -domain, of its large-signal non-quasi-static equivalent circuit, and its predictions are compared with circuit simulation results for buffered differential pairs and Active Pulldown ECL (APD-ECL) inverters.

The perforated emitter contact effect

A new phenomenon, the perforated emitter contact effect, is described. It arises when numerous extremely small gaps or perforations are introduced to an interfacial oxide layer in the emitter region of a bipolar transistor. Two-dimensional simulation of a novel emitter structure that incorporates a perforated interfacial layer indicates that such a layer can provide significant current gain enhancement with a negligible increase in series emitter resistance. These results have implications for polysilicon emitter bipolar transistors and suggest that significant tradeoffs between emitter resistance and current gain can conceivably be obtained if an intentionally grown interfacial oxide layer is thermally annealed so as to break up the oxide just enough to create numerous small perforations.<<ETX>>

Non-quasi-static modeling of neutral region a.c. photo currents in integrated photodiode detectors

Abstract The functional dependence of the magnitude of a.c. photo currents arising in charge neutral regions of silicon integrated photodiode detectors is studied by way of numerical small signal analysis. The analysis shows for typical integrated structures, which are compatible with standard bipolar transistor technology, that a significant portion of the a.c. photo current is generated within the surface and buried quasi-neutral layers and must be taken into account for complete a.c. characterization of the diode. A simple non-quasi-static expression is developed which is shown by comparison with a.c. numerical simulation to accurately model the response of the photo current from neutral regions to light signal modulation frequency.

Partitioned-charge-based BJT model using transient charge control relations for arbitrary doping and bias conditions

Recent transient charge control (TCC) relations such as the TICC or more general GTCC are applied to accurate calculation of base charge partitioning for arbitrary doping profiles and bias conditions. A large-signal BJT circuit model is developed using this approach; both DC and complete first-order AC characteristics are derived from static device simulations. >

Impact of the emitter and base diffusion capacitances on the a.c. behavior of bipolar transistors

Abstract The influence of stored minority carrier charge in the emitter and base regions of a bipolar transistor on the small signal a.c. behavior is studied using small signal a.c. numerical simulation. The validity of the quasi-static approach to correctly model the contribution of the emitter diffusion capacitance to the small signal a.c. response, particularly in polysilicon emitter bipolar transistors, is assessed. It is shown that the onset of non-quasi-static behavior in the emitter of polysilicon emitter bipolar transistors can greatly reduce the impact of the emitter diffusion capacitance on the frequency response of the transistor. An analytic expression is presented which can model the impact of non-quasi-static effects in the emitter on the a.c. common emitter current gain, and which involves only quantities that can be obtained from a d.c. analysis.